ASIC SoC Verification Engineer

YOGINATH GANDITI

ASIC DESIGN VERIFICATION ENGINEER SoC VERIFICATION EMBEDDED SYSTEMS

SUMMARY

ASIC Design Verification Engineer with 3+ years of experience supporting ASIC, SoC, and embedded system validation across verification and hardware environments. Hands-on experience with SystemVerilog, UVM, constrained-random testing, functional coverage, assertions, and RTL simulation using Synopsys VCS and Cadence Xcelium. Skilled in AMBA AXI/APB verification, waveform debugging, regression analysis, and Python/Shell automation in Linux environments. Strong background in hardware-software integration and cross-functional debugging. PROFESSIONAL EXPERIENCE

ASIC Design Verification Engineer Draper USA Jan 2026 – May 2026

• Supported ASIC and SoC verification activities by maintaining UVM-based environments and developing SystemVerilog test scenarios for assigned RTL blocks, improving regression consistency across ongoing verification cycles.

• Developed UVM sequences, drivers, monitors, and scoreboards to exercise functional scenarios and improve reusable verification components, enabling more consistent validation across assigned IP blocks.

• Created constrained-random and directed test cases for functional and corner-case scenarios, increasing functional coverage from 80% to 92% for targeted verification areas and supporting coverage closure before milestone reviews.

• Verified AMBA AXI and APB interfaces through protocol-focused simulations and transaction-level checks, analyzing unexpected DUT behavior and helping identify interface and RTL functional mismatches.

• Executed Synopsys VCS and Cadence Xcelium regressions in Linux environments, reviewed failed simulations, and collaborated with senior verification engineers to reduce repeated regression reruns by approximately 20%.

• Debugged RTL and testbench failures using Verdi and DVE waveform analysis, tracing signal and transaction behavior to isolate functional mismatches and accelerate root-cause analysis during verification cycles.

• Implemented and maintained SystemVerilog assertions and functional coverage models for assigned design features, improving visibility into protocol violations and corner cases while supporting verification coverage closure.

• Developed Python and Shell scripts for regression log parsing, simulation monitoring, and automated report generation, reducing repetitive verification tasks and improving the efficiency of daily regression analysis.

• Assisted with low-power and reset verification by validating reset sequences, clock-gating behavior, and UPF-aware simulation scenarios, helping identify power-management and initialization issues before verification milestones. Embedded Engineer Continental India July 2021 – Nov 2023

• Developed embedded firmware for ARM Cortex-based microcontrollers using Embedded C, enabling efficient processing of real-time data and improving system throughput by 30% in telecom and IoT-based applications.

• Designed and implemented low-level device drivers for UART, SPI, CAN, and GPIO interfaces, improving hardware communication reliability by 33% and reducing transmission errors in embedded systems.

• Worked on Embedded Linux kernel modules and driver development, enhancing system performance and reducing kernel-level latency by 22%, ensuring stable operation across hardware platforms.

• Performed debugging and troubleshooting using JTAG, GDB, and logic analyzers, identifying and resolving critical firmware defects, which improved system reliability by 27%.

• Collaborated with cross-functional teams including hardware engineers and QA teams to validate embedded systems, ensuring compliance with design specifications and reducing post-deployment issues by 24%.

• Implemented power management strategies and memory optimization techniques, reducing system resource usage by 20% and enhancing performance in constrained environments.

• Developed automated test scripts using Python for firmware validation, reducing manual testing efforts by 35% and improving testing efficiency and accuracy.

• Supported system integration and validation activities, including hardware-software interaction testing, leading to improved product stability and faster deployment cycles.

• Followed Agile methodologies and participated in sprint planning, code reviews, and continuous integration processes, improving development productivity and reducing delivery timelines by 18%. TECHNICAL SKILLS

• Programming Languages: SystemVerilog, Verilog, C, C++, Embedded C, Python, Bash/Shell

• ASIC & SoC Verification: RTL Verification, Functional Verification, IP Verification, SoC Verification, Constrained-Random Testing, Directed Testing, Regression Testing

• UVM & Verification: UVM, Testbench Development, Sequences, Drivers, Monitors, Scoreboards, SystemVerilog Assertions, Functional Coverage, Code Coverage, Coverage Closure

• Simulation & Debugging: Synopsys VCS, Cadence Xcelium, Synopsys Verdi, DVE, Linux, Waveform Analysis, Simulation Debugging, Root Cause Analysis

• Protocols & Interfaces: AMBA AXI, APB, UART, SPI, I2C, CAN, GPIO, USB

• Embedded Systems: ARM Cortex-M, ARM Cortex-A, Embedded Linux, RTOS, Firmware Development, Device Drivers, Hardware-Software Integration

• Debugging & Hardware Validation: JTAG, GDB, Logic Analyzer, Oscilloscope, Hardware Bring-Up, Hardware Validation

• Automation & Development Tools: Python Scripting, Shell Scripting, Regression Automation, Log Parsing, Git, Make, CMake, Jenkins, CI/CD

• Performance & System Optimization: Memory Management, Latency Optimization, Power Management, Embedded System Optimization

• Methodologies & Standards: Agile/Scrum, Code Reviews, Continuous Integration, MISRA C, ISO 26262 HONORS

Provost's Award for Research Excellence – 2nd Place Engineering & Computer Science Graduate Research Symposium California State University, Sacramento (2026)

RESEARCH PROJECTS

Radar Signal Classification Pipeline 2025 – 2026

• Developed MATLAB and Python signal-processing pipelines implementing FFT, Range-Doppler processing, CFAR detection, and feature extraction.

• Optimized radar algorithms for embedded deployment achieving 93% classification accuracy with near real-time performance. RF & mmWave Radar Receiver Platform 2025 – 2026

• Architected and validated a 60 GHz mmWave radar sensing platform for continuous human gait monitoring.

• Developed embedded data acquisition pipelines integrating RF front-end, ADC capture, synchronization, and MATLAB/Python-based signal processing.

• Implemented FFT, Range-Doppler processing, CFAR detection, and clinician-facing gait metrics.

• Evaluated radar performance across more than 20 human subjects, improving receiver fidelity by approximately 18%.

• Contributed to an MDPI Sensors journal publication and an IEEE ICHI conference paper. USA +1-408-***-**** ********.*@**************.*** LinkedIn Shoe-Mounted mmWave Radar SoC - RF Receiver Characterization 2025 – 2026

• Designed an RF receiver signal chain including RF conditioning, IQ down-conversion, and Range-Doppler processing using the BGT60TR13C mmWave Radar SoC.

• Developed receiver calibration methodologies correcting inter-antenna gain and phase mismatch, with concepts transferable to 5G NR FR2 phasedarray receiver validation.

RF Hyperthermia TX/RX Characterization & Multi-Antenna Interference Mitigation 2024 – Oct 2025

• Co-developed a MATLAB-based Treatment Planning System incorporating SAR and E/H-field computation for RF hyperthermia treatment optimization.

• Optimized antenna placement and reduced unwanted focal heating through iterative multi-antenna tuning techniques analogous to beam steering and interference mitigation in wireless communication systems. RF Receiver Characterization & Hardware Validation 2025 – 2026

• Characterized RF receiver performance including receiver sensitivity, gain, dynamic range, and noise figure using spectrum analyzers and signal generators.

• Developed MATLAB automation workflows reducing RF characterization setup time by approximately 40%.

• Performed RF calibration, receiver validation, and hardware debugging through systematic root cause analysis. Communication Systems & RF Laboratory Platform 2024 – 2025

• Supported analog and digital communication system development using MATLAB/Simulink.

• Assisted RF Hyperthermia research through transmitter/receiver characterization, system calibration, and experimental validation. EDUCATION

Master of Science – Electrical & Electronic Engineering GPA: 3.65 / 4.00 Jan 2024 – May 2026 California State University, Sacramento, CA

Bachelor of Technology – Electronics & Communication Engineering Aug 2019 – Jun 2023 Sreenidhi Institute of Science and Technology, Hyderabad, India PUBLICATIONS

• First Author - “Millimeter-Wave Body-Centric Radar Sensing for Continuous Monitoring of Human Gait Dynamics,” MDPI Sensors, Vol. 26, Issue 9, 2026. (DOI 10.1109/ICHI69079.2026.00226.)

• Co-Author - “Radar-Based Remote Gait Monitoring with Embedded Data Acquisition and Clinician-Facing Metrics,” IEEE International Conference on Healthcare Informatics (ICHI 2026), Minneapolis, Minnesota. CONFERENCE PRESENTATIONS

• Presented “Radar-Based Remote Gait Monitoring with Embedded Data Acquisition and Clinician-Facing Metrics” at IEEE ICHI 2026.

• Demonstrated a 60 GHz embedded mmWave radar platform featuring RF receiver validation, embedded data acquisition, clinician- facing gait metrics, and radar signal-processing workflows. PROFESSIONAL AFFILIATIONS

IEEE Graduate Student Member

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