Embedded Systems & Edge AI Engineer

KASI VISVANADH PRASADAM

United States ****************@*****.*** 346-***-**** LinkedIn

SUMMARY

Technically rigorous Embedded System Engineer with around 3 years of end-to-end silicon and firmware experience, bridging RTL-to-GDSII physical design with bare-metal and RTOS firmware engineering. Expert in architecting hardware/software co-designs, deploying edge AI (TinyML) onto ARM/RISC-V architectures, and engineering robust UVM verification pipelines to accelerate time-to-market and optimize Power-Performance-Area (PPA) metrics across commercial IoT and consumer SoC platforms. SKILLS

Languages: C/C++, Python, Rust (Embedded), Verilog, SystemVerilog, VHDL, Tcl, Assembly, Bash Embedded Systems & RTOS: ARM Cortex-M, STM32, ESP32, FreeRTOS, Zephyr RTOS, Embedded Linux, Bare-Metal Development, Real-Time Task Scheduling, Multithreading/IPC, Interrupt Handling, DMA, Memory-Mapped I/O, STM32CubeIDE Applied AI Tooling: TinyML/Edge AI Deployment, Python automation, Automated Log, Waveform Analysis Digital Design & Verification: RTL Design (FSM, Pipelining, CDC, Clock Gating), UVM-Based Verification, Testbench Development, SVA, Constrained-Random Testing, Functional Coverage, Formal Verification Basics Interfaces & Protocols: UART, SPI, I2C, CAN, CAN-FD, TCP/IP, USB, BLE/Wi-Fi, GPIO, AXI4/AXI4-Lite, AMBA AHB, PCIe, DDR3/DDR4, NVMe, PCIe

EDA, Simulation & DevOps: Synopsys VCS, QuestaSim, ModelSim, Xilinx Vivado, Git, CI/CD for Embedded (Jenkins/GitHub Actions), Waveform Analysis, JTAG/SWD Debugging

Architecture & Systems: RISC-V, ARM Architecture Basics, Cache & Memory Hierarchy, SoC Fundamentals, Hardware/Software Co-design, Secure Boot/IoT Security Basics

PROFESSIONAL EXPERIENCE

DXC Technology, United States October 2025 – Present Embedded System Engineer

• Architected a secure Bare-Metal to FreeRTOS migration for ARM Cortex-M4, leveraging DMA and Memory-Mapped I/O to bypass CPU bottlenecks, strictly reducing p95 interrupt latency to under 12 microseconds for real-time sensor processing.

• Engineered a highly concurrent BLE and CAN-FD communication bridge utilizing Rust, optimizing TCP/IP packet framing and IPC protocols to guarantee zero message drop across heavily saturated automotive bus networks.

• Deployed quantized Edge AI anomaly detection algorithms (150KB model size) onto an ESP32 cluster using C++ and TensorFlow Lite, cutting cloud telemetry payloads by 60% while maintaining edge inference accuracy.

• Designed thread-safe, non-blocking peripheral drivers within Zephyr RTOS to manage concurrent SPI, I2C, and UART streams, utilizing precise mutexes and real-time task scheduling to prevent resource starvation in edge nodes.

• Optimized data ingestion pipelines by writing highly efficient Assembly routines for memory controllers, maximizing burst transfers and improving system handling up to 15,000 QPS during peak telemetry loads.

• Compiled and customized Embedded Linux device trees via Yocto for STM32 microprocessors, implementing a hardware-backed Secure Boot chain to validate cryptographic signatures and block unauthorized firmware rollbacks.

• Built an automated CI/CD pipeline using GitHub Actions and Bash scripting to trigger regression test suites, seamlessly integrating JTAG/SWD hardware-in-the-loop (HIL) testing to drastically accelerate firmware integration cycles. Dixon Technology, India June 2022 – July 2024

Verification Engineer

• Developed a comprehensive UVM-based verification environment with SystemVerilog for custom AXI4/AXI4-Lite memory controllers, achieving 100% functional and code coverage closure across rigorous constrained-random test suites.

• Performed exhaustive formal verification and deployed complex SystemVerilog Assertions (SVA) on an in-house open-source RISC-V processor, mathematically proving instruction set compliance and eliminating critical pipeline flush vulnerabilities.

• Architected specialized testbenches to stress-test asynchronous FIFO boundaries, isolating and resolving 12 critical clock-domain crossing (CDC) synchronization bugs before initial silicon tape-out.

• Automated waveform analysis and verification debugging pipelines using Python and Tcl scripting hooked directly into QuestaSim, parsing simulation logs to rapidly identify root causes for complex finite state machine (FSM) deadlocks.

• Scaled regression testing environments by feeding massive randomized datasets (over 50GB of simulated network traffic) into Ethernet MAC Verification IP, validating sustained throughput limits under edge-case network congestion.

• Engineered custom Bash and Python plumbing scripts to seamlessly bridge Synopsys VCS simulation outputs with centralized tracking dashboards, providing real-time visibility into verification progression and failure categorization.

• Led top-level SoC integration verification for a smart metering platform, running comprehensive gate-level simulations with SDF back-annotation to guarantee functionality across all operational voltage and temperature corners. EDUCATION

Master of Science in Electrical and Computer Engineering August 2024 – May 2026 University of Houston, Cullen College of Engineering, Houston, Texas Coursework: Advanced Digital Design, Hardware Verification, Hardware Design, VLSI Design, CMOS Analog Integrated Circuits, Advanced Computer Architecture, Advanced Process Integration for VLSI, Advanced Topics in MOS Devices, Integrated Circuit Engineering

Bachelor of Technology in Electrical and Electronics Engineering August 2020 – May 2024 Vignan Institute, Guntur, India

PROJECTS

RTL-to-GDSII Implementation and Signoff of PicoRV32 RISC-V Core

• Executed physical design flow using Cadence Innovus, including floorplanning, placement, routing, and timing closure at 100 MHz.

• Performed signoff checks (DRC/LVS, IR drop, power analysis) and automated flows using Python/Tcl, achieving optimized PPA and violation-free design.

ROM-Based Secure Access Control and Real-Time Game System on FPGA

• Verified an FPGA system with ROM-based authentication and FSM control using SystemVerilog testbenches across modules.

• Validated timing, control logic, and edge cases through directed simulations and real-time FPGA testing. AXI4 Protocol Verification Using UVM

• Developed a UVM testbench with monitors, scoreboards, and checkers to verify AXI4 protocol and handshake mechanisms.

• Executed constrained-random testing and regression suites, achieving coverage closure through debugging and assertion analysis.

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