FPGA/RTL & Embedded Communication Systems Intern

Nguyen Phi Quoc Bao

FPGA/RTL & Embedded Systems for Communication Applications

Date of Birth: 08 Dec 2005

Gender: Male

Phone: 036*******

Email: *******.******@*****.***

GitHub: https://github.com/quocbao1233333

Address: 17 Street No. 7, Linh Trung Ward, Thu Duc City, Ho Chi Minh City, Vietnam GPA: 2.85

CAREER OBJECTIVE

Electronics and Telecommunications Engineering student focused on FPGA/RTL design and embedded systems for communication applications. Seeking an Internship/Fresher position in FPGA/RTL or Embedded Engineering. Hands-on experience with Verilog HDL, Xilinx Vivado, PYNQ-Z2, AXI interfaces, C/C++, Python, MATLAB, and hardware-software integration through projects in modulation classification, FPGA DSP, neural-network acceleration, and ESP32-based AIoT systems. Aiming to strengthen RTL design, digital signal processing, hardware debugging, and real-world embedded communication system implementation.

EDUCATION

2023 - 2027 Ho Chi Minh City University of Technology and Education (HCMUTE) B.Eng. in Electronics and Telecommunications Engineering Relevant coursework: Digital Electronics, Microprocessors, Verilog HDL/FPGA, Digital Communications, Digital Signal Processing, Embedded Systems, IoT.

HONORS & AWARDS

2026 Project Team Leader - UAV IoT

Led a research team developing a UAV-assisted IoT data collection system using Double Deep Q-Network (DDQN) to optimize 3D flight trajectories; reached the final round of the 14th Design, Manufacturing and Application Award in 2026.

PERSONAL PROJECTS

2026 Quantized MLP Accelerator for Automatic Modulation Classification on PYNQ-Z2 Technologies: PYNQ-Z2, Verilog HDL, Xilinx Vivado, Python, PyTorch, AXI4-Lite, Fixed-Point Implemented a quantized MLP accelerator for BPSK, QPSK, QAM16, and GFSK classification, from model training and quantization to RTL and custom IP integration.

2023 - 2024 OFDM Transceiver System using Verilog HDL on Vivado Technologies: Verilog HDL, Xilinx Vivado, OFDM, 16-QAM, FFT/IFFT, AWGN Channel, Testbench Designed an OFDM transceiver supporting 16-QAM, 8-point FFT/IFFT, cyclic prefix, channel estimation, and equalization; verified I/Q waveforms and data recovery with testbenches. 2026 FPGA FIR Filter IP Core on PYNQ-Z2

Technologies: Xilinx Vivado, PYNQ-Z2, FIR Compiler, AXI DMA, AXI4-Stream, System ILA, Jupyter Built an FPGA FIR filtering pipeline with AXI DMA/AXI4-Stream, verified time/frequency-domain results in Jupyter, and debugged streaming signals using System ILA.

2026 RTL-Based 1-D CNN Accelerator for ECG Classification on PYNQ-Z2 Technologies: Verilog HDL, Xilinx Vivado, PYNQ-Z2, AXI BRAM, AXI GPIO, Jupyter, MMIO Implemented a lightweight 1-D CNN accelerator with RTL datapath/control, BRAM/GPIO interfaces, and Jupyter MMIO tests for hardware-software verification.

2026 ESP32 AIoT Monitoring and Alarm Control System Technologies: ESP32, C/C++, Arduino IDE, Wi-Fi, WebSocket MCP, DHT11, OLED, GPIO Developed real-time temperature/humidity monitoring with OLED display, LED/buzzer alarms, and remote control through an AIoT chatbot interface.

CERTIFICATIONS

04/2026 CS402: Computer Communications and Networks - Saylor University Certificate of Achievement, 38 hours, Grade: 86.54%, Certificate ID: 5004129503PN. 04/2026 Electronic Applications - OpenLearn, The Open University Statement of Participation, 10-hour course on communications, control, signal processing, and digital signal processing.

SKILLS

Problem Solving Analyze technical issues using waveforms, testbenches, simulation logs, and system diagrams; experience debugging RTL port/parameter issues, UART communication, and sensor data. Technical Skills Verilog HDL, Xilinx Vivado, PYNQ-Z2, AXI4-Lite/AXI4-Stream, MATLAB, Cadence, Qucs-S, Arduino IDE, Python, C/C++, Git/GitHub.

English Able to read technical documentation in Verilog HDL, FPGA, IoT, Computer Networks, Signal Processing, and Computer Vision; basic technical communication in English.

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