Real-Time Embedded Systems & EtherCAT Engineer

Abb Chekfa

P.O. Box ****

Cupertino, CA *****

Cell:408-***-****

*********@*****.***

Summary:

Accomplished Sr. Software Engineer with over 20 years of experience in real-time software development, embedded systems, and hardware/software integration. Expertise in EtherCAT, Hilscher, and Acontis EC-Master protocols, embedded system design, image processing, and debugging. Proven ability to architect and implement scalable software solutions for complex system across various industries, HIL simulation, Strong leadership skills with experience managing cross-functional teams, low level programming, automatic calibration, Cognex firmware, and bug fixing. QNX and Linux RTOS, SIL.

Technical Skills:

• Protocols: EtherCAT, DeviceNet, I2C, SPI, UART, PCIe, USB, Ethernet, RS232, RS485,TCP/IP

• Embedded Systems: Single-wired EFEM, system-level applications, real-time control (QNX, Linux RTOS)

• Programming Languages: C/C++, Python using SWIG, Active Perl

• Software Tools: JSON, OOP, inheritance, multi-threading, CSV configuration

• Applications & Frameworks: Cognex firmware, image processing, pattern recognition, diagnostics tools

• Simulation & Modeling: SoC simulation, hardware communication protocols, time analysis

• Testing & Debugging: System diagnostics, troubleshooting, bug fixing, automatic calibration

• HIL includes Integration of different simulation, module, software component and subsystems into a unified system. Validation ensuring the integrated simulation behaves correctly and meets. requirements. Deployments on real-time to meet test benches., Professional Experience:

Staff System Engineer/Contract at Onto Innovation, Milpitas March 2025-December 2025

• Working on integrating Rorze EFEM. Provided a full interface to move wafer from foup to aligner then to stage. Using Windows, C++.

Sr. R&D Software Engineer at Universal Display Corporation, Santa Clara, August 2023-December 2024

• Architected and implemented a scalable multi-client EtherCAT IO-server using Acontis EC- Master, supporting organic material deposition for large OLED displays. Utilized C++ and OOP principles, with CSV files for scalability.

• Designed and developed a pump server supporting both serial and EtherCAT pumps, including models such as Cryo, Agilent, Shimadzu, and Leybold DV 300. Integrated Python for testing C++ modules.

Sr. Member of Technical Staff at Mattson Technology, Fremont, CA July 2003-August 2023

• Led the integration of EtherCAT Master-slave technology across multiple Mattson products. Developed an adaptable hardware layer for auto-detecting EtherCAT master/slave configurations, supporting backward compatibility.

• Engineered a scalable wafer scheduler for next-generation products, optimizing wafer handling between EFEM and processing systems. Supported multiple robots and stations using real-time software and multi-threading.

• Spearheaded the development of a single-wired EFEM server controller, responsible for defining communication protocols for both client and server, enabling plug-and-play integration for EFEM types (ASYST-Spartan, BROOKS-fusion).

• Led a team of engineers to migrate wafer strip software from Windows to QNX, optimizing software for higher throughput and multi-node scalability. Designed low-level modules to control hardware (vacuum robots, pressure sensors, heaters) using TCP/IP.

• Provided key training to hardware teams on EtherCAT network configuration using SYCON.net, enabling efficient system setup and maintenance.

Software Consultant at Proteligent, Sunnyvale, CA April 2003- April-2004

• Designed and implemented software enhancements, fixed memory leaks and crashes, led offshore development for the Birdseye network monitoring tool. This real-time multi-threaded application monitored network devices’ connectivity and performance. Sr. Network Software Engineer at Vidtek, Sunnyvale, CA December 2002- April 2003

• Developed a proof-of-concept for a video surveillance system prototype using IP cameras and a WIN2000 server. Implemented CGI for image storage and playback, using Active PERL for real-time image processing.

Taught advanced C in De-Anza college April2002-Jun 2002 Sr. System Engineer/Project lead at Intensys Corporation, San Jose, CA June 2000-July 2001

• Led a team of engineers to design and implement a cycle-accurate SIMD simulator, modeling all components of SIMD architecture. The tool enabled customers to evaluate chip functionality in real-time, HIL, and SLS.

Sr. Software Engineer at Cradle Technologies / Cirrus Logic Inc., Fremont, CA October1997-June 2000.

• Developed a cycle-accurate simulation tool for a new RISC-based chip, supporting multi- chip configurations and programmable I/O. Ensured synchronization with hardware specs for real-time simulation of chip behavior, HIL, and SLS. Sr. Software Engineer at Kla-Tencor/Tencor/Prometrix Co., Santa Clara, CA April 1993-October 1997

• Designed and implemented diagnostic tools for vision systems, improving video calibration and image recognition. Worked closely with manufacturing and field engineers to address customer needs and optimize wafer pattern recognition. Consultant March 1990 -1993

Synergy Computer Graphics Corp, Pixel mapping. Canon Research Center, Worked OCR. Claris Inc,

Part Time Teaching Position, Santa Clara University, CA 1991-1993 Research Assistant, Santa Clara University, CA. 1986-1991 Education:

Ph.D. Computer Engineering finished all but publication, Santa Clara University, CA. Thesis: 3-D Image Reconstruction using a Single Camera MS : Bio-medical Engineering, University of Illinois, IL. Thesis: Design and Implementation of Basic Inspection System Publications:

• “Format Analysis for a Page Reader for the Visually Impaired”, Sally L. Wood and Abdulla Chekfa. Ninth annual Conference of IEEE Engineering in medicine and biology society. Nov. 1987

• “Image Processing Techniques or Analysis and Classification of Page Format,” Abdulla Chekfa and Sally L. Wood. Twenty-first annual asilomar on signal, systems, and computer. Nov. 1987.

ADDITIONAL EXPERIENCE

• Part-time Teaching Assistant – Santa Clara University, CA (1991-1993) Taught advanced C programming and supported lab work for Computer Science students.

• Research Assistant – Santa Clara University, CA (1986-1991) Conducted research in image processing and pattern recognition, contributing to multiple published papers.

LEADERSHIP & TRAINING

• Managed cross-functional teams of 5+ engineers, providing mentorship and driving project execution in high-pressure environments. Delivered EtherCAT network training to hardware teams, enabling efficient system integration and troubleshooting

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