FPGA/SoC Signal Processing Engineer

https://drive.google.com/file/d/*Dh_q*fgPw*RgKvTim0M-vPPPBN7lNjfS/view?usp=sharing

(Transcript)

Cao Khanh Duy

FPGA/SoC Design Engineer Open to Part-time & Remote Projects

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CAREER OBJECTIVE

Passionate about developing real-time projects on FPGA/SoC platforms and officially graduating in October 2026. Currently engaged in the industry as a Signal Processing Engineer, I am exclusively seeking part-time or remote opportunities where I can apply my FPGA/DSP hardware expertise to innovative projects while maintaining my current professional commitments.

EDUCATION

Ho Chi Minh University of Science Expected Oct 2026

Bachelor’s degree in Physics and Engineering Physics

Member PIISA Lab

GPA: 3.56/4.00

Specialized courses: Digital Systems(9.4), IC Design (9.4), Robot Technology and Applications (9.2), Semiconductor

Physics (8.4), Microcontroller (9.2), Fundamentals of Semiconductor Devices (8.9), Solid State Physics (8.9).

PUBLICATION

A real-time FPGA-based vision enhancement system. Submitted to ICEBA 2026 – The 7th International Conference on Engineering, Physics, MEMS-Biosensors and Applications (Under Review)

ACADEMIC EXPERIENCE

Design and implementation of a vision enhancement system on the FPGA DE1-SoC platform [ Completed ] - supervisor Dr. Truong Trung Kien. [ Source ] November 2025 – April 2026

• Platform: Kit DE1-SoC FPGA (Cyclone V), ARM Cortex-A9 HPS.

• Tools & Languages: Verilog HDL, C/C++, Python, Intel Quartus Prime, Qsys/Platform Designer, ModelSim, Matlab, WinSCP, MobaXtern, Linux basic.

• Algorithm: Implemented Dark Channel Prior (DCP) with enhanced transmission map and gamma correction to remove haze, smoke, and fine dust, thereby improving visibility.

• Hardware Acceleration: Designed a multi-stage RTL pipeline for pixel-level image processing at 640 480 resolution, achieving 3.072 ms per frame at 100 MHz.

• Applications: Delivered real-time visual feedback for ADAS, tactical reconnaissance, and robotic vision in harsh environments.

• My graduation thesis was graded excellent with a score of 9.7

Leader-Follower Robotic Arm System [Course: Robot Technology and Applications]- supervisor Dr. Nguyen Dang Duy. [Source ] Nov 2025 – Jan 2026

• Design: Used SolidWorks for 3D modeling, kinematic simulation, and workspace optimization

• Hardware: Built an Arduino-based control loop using Encoders and Servos for real-time operation.

• Control: Implemented mapping algorithms to ensure seamless, low-latency Leader-Follower synchronization.

• Impact: Applicable for remote intervention in hazardous or confined industrial/medical spaces.

Basic People Counting System on DE1 FPGA Technology [Course: Integrated Circuit Design ] - supervisor Dr. Truong Trung Kien.[Source ] 7 days in Nov 2025

• Development Tools & Platforms: DE1- FPGA (Cyclone II), Intel Quartus II (v13.1), Verilog HDL

• Peripherals: IR sensors, LEDs (R/Y/G), 7-segment displays, buzzer.

• System Functions: Hierarchical visual alert system with LED display for occupancy monitoring and overload warnings.

• Applications: Delivered real-time occupancy data to improve operational efficiency, staff coordination, and space management, with potential AI integration for predictive analytics.

WORK EXPERIENCE

Otanics Tomota Joint Stock Company [ AI & Computer Vision Team – Signal Processing Engineer, Ho Chi Minh City]. May 2026 – Present

Smart Feeding Machine — Passive Acoustic Monitoring for Shrimp Aquaculture (In progress)

• DSP Architecture:Designed a multi-stage DSP front-end for hydrophone recordings in aerator-dominated ponds: adaptive comb notch filtering, spectral subtraction, and kurtosis-gated stationary wavelet denoising, reaching ~19 dB SNR on feeding clicks.

• Deep Learning Integration: Implemented spectrogram-based feeding-signal recognition with Faster R-CNN, tuned for sub-millisecond acoustic events.

• Control Systems: Designed a fuzzy logic controller driving automated feeder actuation from acoustic activity indicators.

• Predictive Modeling:Built a regression model predicting per-cycle feed consumption from acoustic features and dispensed feed mass.

SKILLS

• HDL & RTL Design: Verilog HDL, SystemVerilog, RTL pipeline design, FSM, datapath/control design, fixed-point arithmetic, resource–throughput tradeoff.

• Verification & Timing:ModelSim, testbench development, waveform debugging, static timing analysis (TimeQuest), timing closure, SDC constraint writing.

• FPGA Toolchain & Flow: Intel Quartus Prime, Qsys/Platform Designer, IP integration, PLL configuration, Vitis HLS

• Embedded & SoC: ARM Cortex-A9 HPS, HPS–FPGA bridge, memory-mapped I/O, DMA controller design, embedded Linux, bare-metal C

• DSP Hardware: Line-buffer/sliding-window architecture, pixel-level streaming pipeline, FIR/IIR filter design, real-time frame processing, VGA controller

• Signal & Image Processing: STFT/spectrogram analysis, spectral subtraction, wavelet denoising (DWT/SWT, thresholding), adaptive filtering, FIR/IIR design, transient/impulsive signal detection, Dark Channel Prior (DCP) dehazing.

• Programming Languages: Python, C++, Verilog HDL.

• Deep Learning: CNN architectures (ResNet, VGG, MobileNet), PyTorch, Faster R-CNN, YOLO

• Languages: IELTS 5.5

AWARDS

• Second Prize in the Provincial Geography Contest, Ca Mau (2021, 2022),Bronze Medal at the 30/4 Olympiad in Geography (2021).

• Consolation Prize in the Provincial Science and Engineering Fair, Ca Mau (2022) and 5-time recipient of the merit scholarship for the Ca Mau Math-Informatics specialized class.

• Awarded Outstanding Academic Encouragement Scholarship for both semesters, Academic Year 2025–2026.

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