RF Test Automation Engineer

Sandeesh Reddy Polamreddy

San Francisco, CA • 510-***-**** • *.*************@*****.*** • linkedin.com/in/sandeesh-reddy-polamreddy SUMMARY

Test & Automation Engineer with an M.S. in Electrical & Computer Engineering and 2+ years developing automated test software

(Python, SCPI, MATLAB/Simulink) integrated with RF and electronic lab equipment, including spectrum analyzers, signal generators, and vector network analyzers. Skilled in data acquisition, calibration, and measurement-accuracy validation, with proven ability to troubleshoot and extend existing codebases with limited documentation. Experienced supporting both sustaining test systems and new product introductions, collaborating across cross-functional engineering teams, and producing clear technical documentation for hardware and software test methods.

TECHNICAL SKILLS

• Test Automation & Software: Python, MATLAB/Simulink, LabVIEW, SCPI, Automated Test Software Development, Data Acquisition & Analysis, Regression Automation, Git, Jira, Make

• Test Equipment Integration: Spectrum Analyzers, Signal Generators, Vector Network Analyzers (VNA), Oscilloscopes, Lab Instrumentation, Equipment Calibration & Path-Loss Compensation

• RF & Hardware Validation: Multi-GHz RF Testing (LTE, 5G NR FR1), Signal Integrity, FPGA/Embedded Hardware Bring-Up, PCB-Level Debug

• Protocols: SPI, I2C, UART, MIPI, Ethernet, Wi-Fi

• Design Verification (secondary): SystemVerilog, UVM, Constrained-Random & Coverage-Driven Verification, Static Timing Analysis (Synopsys PrimeTime)

• AI-Assisted Tooling: LLM-driven test generation, AI-assisted debug & root-cause analysis, evaluation harnesses & benchmarks PROFESSIONAL EXPERIENCE

RF Hardware Test & Validation Engineer — UL Solutions Mar 2026 – Present

• Develop Python/SCPI-based automated test software to execute and report multi-GHz RF test sequences (LTE, 5G NR FR1), replacing manual procedures and standardizing pass/fail evaluation against internal specifications.

• Integrate test automation with spectrum analyzers, signal generators, and vector network analyzers (VNAs) to validate measurement accuracy and isolate signal-integrity and compliance issues at the component level.

• Build calibration and path-loss compensation routines that maintain data quality and measurement accuracy across high-precision test apparatus.

• Serve as technical point of contact for lab operations, documenting test status, defects, and corrective actions for multidisciplinary engineering teams.

Embedded Software Trainee — Keyphase Inc Nov 2025 – Feb 2026

• Supported bring-up and troubleshooting of microcontroller-based prototypes, diagnosing low-level driver and peripheral-interface issues in existing codebases with limited documentation. FPGA & Embedded Systems Engineer — KPIT Technologies Oct 2021 – Nov 2022

• Executed hardware bring-up and validated electromechanical control logic for FPGA-based subsystems, verifying functional behavior against design intent.

• Performed root-cause analysis of interface-level signal-integrity issues and debugged serial bus transactions (I2C, SPI, UART) using lab instrumentation.

• Reviewed PCB layout constraints with design teams and aligned hardware specifications for prototype builds. PROJECTS

AI-Assisted Test Automation & Evaluation Harness

• Built a Python evaluation harness integrating LLMs to automate root-cause analysis of simulation and hardware test failures and to validate AI-generated test cases against reference results.

• Engineered labeled benchmarks and acceptance criteria to measure test-quality and data accuracy, producing a reusable methodology playbook.

• Developed a regression-triage dashboard that clusters failures and surfaces recurring hardware/software issues, reducing manual debug and analysis time.

Static Timing Analysis & ASIC Implementation — Synopsys Flow

• Performed full-chip static timing analysis on a 14nm CMOS design using Synopsys PrimeTime, defining clock, I/O, and exception constraints (SDC) and validating setup/hold timing across process corners.

• Diagnosed and resolved setup and hold violations on critical paths through timing ECOs and constraint refinement, driving the design to full timing closure.

EDUCATION

M.S., Electrical & Computer Engineering — San Francisco State University Aug 2025 Relevant coursework: LabVIEW-based data acquisition and instrument control projects B.E., Electrical & Electronics Engineering — RMD Engineering College May 2022

Contact this candidate