Senior Process Development & NPI Engineer

Xiaozhou "Joe" Yu, Ph.D.

Senior Process Development Engineer Process Integration NPI Semiconductor Manufacturing

Fremont, CA ***********@*****.*** 205-***-****

PROFESSIONAL SUMMARY

Senior Process Development Engineer with 6+ years of semiconductor R&D, process integration, and new product introduction (NPI) experience spanning advanced thin-film deposition, process optimization, and manufacturing scale-up for next-generation memory and logic technologies. Proven track record of leading cross-functional development from early R&D through customer qualification, technology transfer, and production readiness. Strong expertise In DOE, statistical process control (SPC), root cause/failure analysis, yield improvement, and hardware optimization. Ph.D. in Chemical Engineering with hands-on semiconductor device fabrication experience spanning CMOS, lasers, and photodetectors— looking to bring this process-development and NPI rigor to advanced packaging and co-packaged optics manufacturing.

TECHNICAL EXPERTISE

●Process Development & NPI: process development & integration, new product introduction (NPI), manufacturing readiness, technology transfer, production ramp support, design of experiments (DOE), statistical process control (SPC), root cause analysis (RCA), failure analysis, yield improvement

●Semiconductor fabrication process: CVD, ALD, PVD, ALE, RTA, CMP, etching, lithography, plasma processing, metal fill, barrier/liner engineering, contact & interconnect integration

●Characterization & Metrology: SEM/EDX, TEM, EELS, AFM, XPS, XRD, XRF, PL, ellipsometry

●Software & Data Analysis: JMP, Python, SolidWorks, AutoCAD, MATLAB, LabVIEW, Origin

WORK EXPERIENCE

ASML, Performance and Integration Department, San Jose, CA

Senior Application Development Engineer April 2025 – Present

Product & Process Development for Next-Generation E-Beam Inspection Platform

●Led process development and customer application enablement for a next-generation e-beam inspection platform supporting advanced semiconductor manufacturing, delivering a 50% throughput improvement through scan methodology redesign, software feature development, and hardware CIP initiatives.

●Invented a high-resistance defect detection algorithm that improved defect sensitivity, enabling earlier process-excursion detection and faster yield learning for advanced memory technologies.

●Developed and deployed a machine learning-driven Automated Defect Classification (ADC) platform, achieving 90% classification accuracy while reducing defect review time by 30%.

●Collaborated with cross-functional software, hardware, and customer engineering teams to deliver production-ready inspection solutions, supporting NPI and process validation activities across multiple technology nodes.

Applied Materials, Inc., Metal Deposition Products Group, Sunnyvale, CA

Senior Process Development Engineer (Process Engineer III-- Senior Process Engineer) Feb 2020 – Nov 2024

Led next-generation CVD tungsten (W) process and integration development for ultra-high-aspect-ratio (UHAR) metal contacts in advanced 3D NAND and DRAM technology.

●Led development of next-generation CVD tungsten process for UHAR metal contacts, supporting new product introduction, customer qualification, technology transfer, and manufacturing readiness for advanced 3D NAND production.

●Invented and patented a gas-phase growth-suppression CVD W process enabling seamless void-free gap-fill in extreme HAR (>100:1) structures; validated with tier-1 memory customers and supported tool start-up and process transfer from R&D into customer manufacturing environments.

●Established qualification criteria, DOE, and process control plans, partnering with hardware and integration teams to optimize chamber architecture, heater geometry, and thermal control— improving film uniformity and reducing the cost of ownership (CoO).

●Defined process windows and executed statistical DOE studies to optimize contact resistance, void-free fill, throughput, and process robustness across customer technology nodes.

Advanced Process Development — plasema based Seam Suppresserd CVD Tungsten (W) deposition

●Led end-to-end process development for advanced logic and memory metal contacts— from precursor and hardware evaluation through prototype validation and Phase 4 (limited HVM) qualification— full ownership of the NPI lifecycle.

●Secured Process Tool of Record (PTOR) positions with 1st-tier memory customers by delivering superior gap-fill performance, reliability, and scalability.

●Performed root-cause failure analysis (SEM/EDX), gas-line partition testing, and reaction modeling to eliminate particle contamination and improve chamber cleanliness and film quality.

●Reduced hardware cost by 50% in Remote Plasma Source (RPS) through an innovative plasma cavity coating process that improved ignition stability and extended hardware lifetime.

CVD Ruthenium (Ru) Process Development and Mechanism Study

●Pioneered bottom-up CVD Ru deposition for middle-of-line (MOL) applications using gas-phase inhibitors, enabling conformal, void-free fill in high-aspect-ratio structures.

●Designed and integrated multi-step surface preparation flows (APC, H /N plasma, eAPC, and post-surfactant degassing) to achieve high nucleation selectivity and interface cleanliness.

The University of Alabama, Department of Chemical Engineering, Tuscaloosa, AL

Ph.D. Program Graduate Research Assistant Jan 2015 – May 2019

●Developed ALD thin-film deposition processes using a custom-built reactor with advanced in-situ diagnostics (FTIR, QCM, and QMS) to understand precursor adsorption, surface reaction mechanisms, and film growth kinetics.

●Engineered ultra-thin oxide encapsulation layers (ZnO, TiO, Al O ) for optoelectronic (perovskite) devices to optimize interface quality and film conformity, extending device lifetime from days to months— direct thin-film experience on photonic/optoelectronic device structures.

EDUCATION

●Ph.D. in Chemical Engineering, The University of Alabama, Tuscaloosa, AL, May 2019

●M.S. in Polymer Materials, Dalian University of Technology, Dalian, China, July 2014

●B.S. in Polymer Materials and Engineering, Dalian University of Technology, China, July 2010

SELECTED PATENTS AND PUBLICATIONS (2 of 10)

●Li Y, Wang P, Wu K, Lu D, Yu X, Ha I, and Meng Z. Growth Suppression Deposition for CVD Tungsten Gap Fill with Thermal Treatment; US Patent: 44023591US01

●Yu X, Yan H, and Peng Q. Improved Stability of Hybrid Halide Perovskite via Atomic Layer Deposition on Activated Phenyl-C61 Butyric Acid Methyl Ester. ACS Appl. Mater. Interfaces, 2018, 10 (34), pp 28948–28954.

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