Asic Design Verification Engineer

Avnish Niranjan Jani (BE, MS)

Email: ****.******@*****.***

Phone: +91-999**-*****

Summary:

•Self-Motivated, Result Oriented, Creative and Quick Learning ASIC Design Verification Engineer with 5 years of total IT Experience.

•IP and SOC verification. Have very good experience in creating test cases, test plans, writing test benches in Verilog and System Verilog. Also have experience in finding bugs in the design and fixing them in the design.

•Architected the class-based verification environment using system Verilog.

•HDL module design, Simulation/Synthesis/Optimization of HDL modules in design tools like Synopsys/Cadence/Xilinx /Modelsim.

•Have exposure to DFT (BIST, Boundary Scan, etc.) and Back End (Physical Design) Software Tools for Back-end Design like DRC, LVS, ERC, Floor Planning, Optimizations for Power and Area till Fabrication of the Physical Chip and after that Emulation with Test l test vectors and Sign off from the ASIC Design Cycle.

•Created Script files using PERL and Shell, to link the Test bench along with the DUT with the Test Environment and for other connections via OS.

•Well versed with the protocols (High Speed Bus Protocols (AXI 4.0), Cache Coherency Protocols, etc.), Design and Verification.

•Knowledge on SOC Verification, have knowledge in creating a test environment for Verification of SOCs.

•Created Micro code module for RISC CPU, MIPS 32-Bit pipelined processor and Bi-directional bus using FPGA, Schematic Capture/Simulation of MOS Op-Amp in P-Spice with current mirror.

•Also have complete and comprehensive knowledge of Multicore processor architecture and Multiprocessor architecture.

•Complete knowledge of different cache coherency protocols for Multiprocessor system architecture.

•Excellent experience in organizing projects, writing technical reports and problem solving.

Technological Expertise:

Operating Systems: UNIX, Windows

HVL: Verilog, VHDL, System Verilog, UVM

Design Tools: VCS, Altera MaxPlus II, Xilinx Design Manager, Modelsim, Synopsys Design Analyzer, P-Spice,

MATLAB, LAB VIEW

Software Languages: C, C++, Assembly (8086)

Bus Protocols Known: AMBA AXI 4.0

Knowledge of cores& CPUs: ARM cores& CPUs (ARM-v7A, ARM-v8A), Cortex-A9

Memory Coherence protocols: Snoop Based (MESI, MOSI, and MOESI), Directory Based

VLSI Experience:

Parul University. Apr 2024 – Oct 2024

NISG Oct 2023 – Jan 2024

Expleo, Bangalore Nov 2021 - Dec 2021

Aricent, Bangalore May 2018 – Jul 2018

HCL, Noida Apr 2017 – Aug 2017

Wipro, Pune Jun 2011 – Jan 2012

Silicon Interfaces, Mumbai Jul 2009 – Jul 2009

Embassys, Ahmedabad Oct 2007 – Apr 2008

Printed Circuit Corp, USA Oct 2006 – Nov 2006

IT Experience:

Delasoft, Delaware, USA Jan 2007 – Apr 2007

AK Systems, Baroda Nov 2005 – July 2006

Academic Experience (Instructor/Project Guide/Lecturer/Assistant Professor):

Sigma Institute of Engineering, Baroda Jul 2012 – Dec 2014

DD Institute of Technology, Nadiad Mar 2005 – Nov 2005

DD Institute of Technology, Nadiad Jan 2001 – Jun 2001

Netvision India Private Limited, Vadodara May 2000 – Nov 2000

Work Experience:

Parul University. Apr 2024 – Oct 2024

Role: Assistant Professor in CSE Department

NISG (NATIONAL INSTITUTE FOR SMART GOVERNMENT) Oct 2023 – Jan 2024

Role: Aerospace Hardware Senior Specialist

Client: DRDO, Bangalore

Department: CASDIC (COMBAT AIRCRAFT SYSTEM DEVELOPMENT AND INTEGRATION CENTRE)

Project Name: ATMARAKSHAK

Brief Functional Description: Development of Key Functional Features of the Aircraft.

Technological Responsibilities:

●Programming of Acra KAM-500 using the software K workbench.

Expleo, Bangalore Nov 2021 - Dec 2021

Role (Designation) in the Company: Engineer

Project Department: AVIONICS

Project Client: Mercury Systems, Geneva, Switzerland

Brief Functional Description:

VIP Qualifying Assessment of AVIONICS IP VIPs. There were about 8 VIPs needed to be assessed given by the Client Mercury Systems.

Aricent, Bangalore May 2018 – Jul 2018

Role in the Company: Engineer V2 Grade

Brief Functional Description:

Was hired by ARICENT, for the Engineer V2 position in the company as ASIC IP Verification Engineer. Was supposed to work for the client project at client place for ASIC IP Design Verification Projects. Was interviewed by 2 clients, 2 rounds each. The company management was cutting of some workforce from the company due to company policy, happened to be one of them and got relived by company management on 27 July 2018.

Technological Work performed during work Tenure:

•Had technological discussion with colleagues in the company on SV UVM and brushed up the System Verilog and UVM Fundamentals along with other fellow company employees who were on ODC project works in the company and discussed about their project work that they were doing.

•Had discussion session on High-Speed Data Bus AXI 4.0 with the Verification Test cases.

HCL, Noida Apr 2017 – Aug 2017

Role in the Project: Lead Engineer

Project Name: SRAM Memory Controller Verification

Client Name: Renessa, Japan.

Brief Functional Project Description:

The project was to verify the SRAM Memory Controller. The verification IP, AXI VIP, was already bought from Synopsys. We were a 5 members team to verify the SRAM Memory Controller, each were allocated around 11 test cases to develop provided according to the different features of the operation (Functionalities) of SRAM Controller according to the scenarios provided by the client. Along with the test cases the team members were supposed to develop the Scoreboard (\Checker) and the Coverages module for the test bench. In my part, I was given 11 test cases to verify the operations (Functionalities) of the Control Registers of the Memory Controller. In addition to the development of the test cases and the Scoreboard with Coverage module, I was to communicate with Synopsys Inc. concerned person for the AXI VIP for the development of our project work to make the test bench compatible to verify the SRAM Memory Controller. The project was to verify the SRAM Memory Controller from the client Renessa, used AXI VIP had every Test bench component in it and needed to modify according to our verification needs of our team that ha around 5 members in the team, each were having about 10-11 test cases. In my part the test cases to verify the internal registers called Control Status Registers. The first test case was to verify the toggling of the CSR last bit that toggle after each successful completion of the transaction/s. The other remaining 10 test cases were about the verification of the other features of the Memory controller using Control Registers. Technological Responsibilities:

•Leading a team for the project.

•Verify the DUT in System Verilog based methodology, UVM.

•Verifying the DUT (SRAM Memory Controller) for the client Renessa, Japan.

•Implementing Checker (\Scoreboard) and Coverage which were supposed to be provided by HCL.

Sigma Institute of Engineering, Baroda July 2012 – Dec 2014 Role in the Institute: Lecturer

Technical Responsibilities:

•Was promoted as a Head of the Department of Electrical and Electronics Engineering

•Used to Manage the Department

•Used to Deliver Lectures to students

Wipro, Bangalore Jun 2011 – Jan 2012

Role in the Project: Systems Engineer Project Name: NSN-GAIA Design Verification Client Name: Nokia - Siemens Networks Brief Functional Project Description:

NSN (Nokia Siemens Networks) - GAIA (Generic Air Interface ASIC) is a chip of interface between an Optical - Fiber and Air. The communication signals of 7 different carriers’ types, like CDMA, LTE, etc., coming from the Optical - Fiber get stored according to the carrier type in the memory first and later get processed inside the GAIA chip and later transmitted in the Air for next processing on the receiving end. The project had many modules, my job was to verify the first two modules that first identifies the carrier type and stores the data (information) after separating the payload data (information) from the ID of the carrier types inside the designated area of the memory according to the carrier type and later the data taken away by the next modules in the process inside the GAIA chip for process ahead. The GAIA chip verification was successful using Verilog Test Bench as well as SV test bench both, the exhausting testing was done for all the combinations of the different test vectors using System Verilog Test bench. The corner cases were verified by Verilog Test bench identifying separately. Both the test results, Verilog and System Verilog, were incorporated and final design was released to the Customer. The coverage for both the results were done using the web based application.

Technological Responsibilities:

•Developed test cases for IF_BB_DL module of NSN_GAIA ASIC in System Verilog.

•Ran regression testing for all the test cases of IF_BB_DL module.

•Modified the test bench of IF_BB_DL module.

Silicon Interfaces, Mumbai July 2009 – July 2009

Role in the Company: Assistant Engineer – VLSI Design

Project Name: ASIC Verification

Brief Functional Description:

The project work was about to be allocated.

Technological Responsibilities:

•ASIC IP Verification using System Verilog.

•Development of the Test bench from scratch.

•Deciding the scenarios and features of the DUT to be verified.

•Scoreboard and Checker along with the decided Coverage.

•To connect the Test bench with the Testing environment, Scripting programs.

Embassys, Ahmedabad Oct 2007 – Apr 2008

Role in the Company: VLSI Design Engineer

Project Name: Device Driver Development Client Name: Embassys

Brief Functional Work Description:

Embassys is a Embedded and VLSI training and Placement company formerly known as Reinfold PIL. Reinfold PIL was a Product Company. Reinfold PIL used to design the protoboards with Xilinx FPGA, Philips ARM and Xilinx CPLD on board. The protoboards are sold to the different industries for their projects and implementations. My job was to develop device drivers in Verilog HDL for the peripheral components around the programmable device on the protoboard, according to their manufacturers and internal mechanisms of the components for their access, communicate and interface with the parallel and synchronized programmable device/s on the protoboard to serve the purpose/s.

Technological Responsibilities:

•Developing device drivers for different components on the protoboards such as serial bus, mouse, keyboard and other components.

•Verify the developed code in Verilog HDL.

Delasoft, Delaware, USA Jan 2007 – Apr 2007

Role in the Company: Software Consultant

Project Name: Automation Testing of ERP software’s

Client Name: MASCO Contractor Services

Brief Functional Work Description:

MASCO Contractor Services is a Construction Company in Florida, USA. My role includes testing ERP software’s like PeopleSoft and Oracle. Used different software testing tools like QTP and Test Manager. Also done Business Process Testing using these tools.

Technological Responsibilities:

•Automate the test cases that are already created for PeopleSoft in QTP.

•Automate the test cases using Business Process Testing for Oracle supply chain management module.

Printed Circuit Corp, USA Oct 2006 – Nov 2006

Role in the Company: Electrical Engineer

Project Name: PCB Fabrication

Client Name: Printed Circuit Corp, Atlanta, Georgia, USA

Brief Functional Work Description:

Printed Circuit Corp is a Atlanta based PCB Design company. The company has enough infrastructure to incorporate and perform the entire process of PCB Design, right from PCB surface forming and metallizing and preparing an alloy for the PCB circuit routing to complete PCB prepared. The process also includes the formation of circuit routes pattern layout using material by pressurizing the material over the PCB surface that acts as a electrically conductive glue for the PCB components mount using specific computer system with components mounting system from different manufacturers available in a reel format. Later down the line the electrically conductive glued components mounted PCB is processed under the furnace that forms the complete PCB, and later the QC is performed over the PCB prepared for the specific project PCB, mainly the undesired shorts of circuit paths, improper formations of circuit paths, etc. were used to be properly checked in QC. My job was to be responsible to perform 3 tasks in the PCB design process, forming a circuit over the PCB of the electrically conductive glued material and forming a circuit electrical paths pattern layout, mounting components over the PCB surface using the computer and mounting mechanism and performing the furnace process that results into complete PCB.

Technological Responsibilities:

•Was responsible to form a circuit electrical path for the particular project using pressure mount electrically conductive glued material over the surface of the PCB and forming a circuit electrical paths pattern layout of the circuit paths over the PCB surface, mounting the electrical and electronic components on the conductive glued surface of the PCB and performing the furnace process over the components mounted PCB.

•Also responsible for the customer interaction about the PCB design project and come up with the optimized PCB design according to the customer needs.

AK Systems, Baroda Nov 2005 – July 2006

Role in the Company: Software Developer

Project Name: Middlesex County website maintenance

Client Name: Middlesex County, NJ, USA

Brief Functional Work Description:

AK Systems is a Software consultancy based in New Jersey, USA and a branch office in Baroda, India. Their main project work is in .Net and JAVA technologies.

Technological Responsibilities:

•Maintenance of website of Middlesex County, NJ, USA.

DD Institute of Technology, Nadiad Mar 2005 – Nov 2005 Role in the Institute: Adhoc Lecturer

Brief Functional Work Description:

DD Institute of Technology is a leading institute for Engineering and Technology. Worked as a Lecturer in the Computer Science Department.

Technical Responsibilities:

•Delivered lectures on the subject of Data Structure and C programming.

•Also conducted final exam as well as Mid-term exams.

DD Institute of Technology, Nadiad Jan 2001 – Jun 2001

Role in the Institute: Adhoc Lecturer

Technical Responsibilities:

•Delivered lectures on the subject of Data Structure and C programming.

Netvision India Private Limited, Vadodara May 2000 – Nov 2000

Role in the Institute: Instructor / Project Guide

Technical Responsibilities:

•Delivered lectures on the subject of C programming and C++ Programming.

Trainings Undergone:

ASIC Verification using System Verilog and VMM Dec 2009 - Jan 2010

Advanced VLSI: ASIC Verification (System Verilog) Oct 2008 – Dec 2008

Embedded Systems Apr 2008 – Sep 2008

Universal Verification Methodology (UVM) Apr 2015 - May 2015

Project Implementation During Training:

Project: AMBA AHB Functional Description:

AMBA AHB is an ASIC (Application Specific Integrated Circuit) performing AMBA AHB Bus Master as Primary Side. It supports Up to 16 Master, in which one acts as a default master. The secondary acts as Slave to the Master. Upon Getting Grant signal from Arbiter the Master Starts transferring the data from Master to Slave with the Corresponding Address and Data from Master to Slave. The Slave will give a response after finishing the transfer transaction.

Technological Responsibilities:

•Involved in Verifying the AHB Master using Verilog HDL.

•Involved in creating test cases to check the transactions.

Project: Dual Port RAM – Verification HVL: System Verilog

EDA Tools: Incisive Enterprise Simulator, RTL compiler and ISE

Technological Responsibilities:

•Implemented the Dual Port Ram using Verilog HDL independently

•Architected the class-based verification environment using system Verilog

•Verified the RTL module using System Verilog

•Generated functional and code coverage for the RTL verification sign-off

Project: Router 1x3 – Verification HVL: System Verilog

EDA Tools: Incisive Enterprise Simulator, RTL compiler and ISE

Technological Responsibilities:

•Implemented the Router 1x3 using Verilog HDL independently

•Architected the class-based verification environment using system Verilog

•Verified the RTL module using System Verilog

•Generated functional and code coverage for the RTL verification sign-off

Academic Projects: Sep 2001 – Dec 2001

Finite State Machine: Designed, Simulated and Implemented Sequence Detector on FPGA in Verilog. Designed a Finite State Machine to solve for a sequence detector using self-clocking and an 8 MHz clock input with 0.18µm technology. Compiled and simulated the design in ALTERA MAXPLUS II.

Designed, Simulated and Implemented Interface between Keypad and LCD Driver using FPGA in Verilog.

To control the duty cycle of the clock using a keypad. Designed a VHDL code to control the intensity of a bank of LEDs at a rate determined by the keypad entry with minimum feature size of 0.18. Also interfaced LCD for stop clock, displaying name and keypad entry.

Interfaced SRAM, ADC and LCD Driver with ALTERA FLEX10k10 FPGA

Instantiated lower-level Verilog modules at top level design. Using Verilog, collected data from ADC and stored them in SRAM. In the next cycle data is displayed in the forward as well as reverse direction using a single Bi-directional Bus.

Designed, Simulated and Implemented micro-code for the RISC CPU in Verilog.

Created micro-code for RISC CPU using four internal registers with limited set of instructions that performs basic operations like Load, Store, Shift, Rotate, Add, Subtract, Increment, etc. The peripheral devices were ADC and LCD.

Created micro code of MIPS 32-Bit 5 stage Pipelined Processor in Verilog.

Designed, Compiled, Simulated and Synthesized 5-stage pipelined MIPS processor in Synopsys VCS and Synopsys Design Analyzer with four basic instructions optimized for time and area.

Educational Qualification:

California State University Sacramento, USA. Aug 2001 – May 2004 Master of Science in Electrical and Electronics Engineering with specialization in VLSI Technology

Gujarat University, India Nov 1996 – May 2000

Bachelor of Engineering in Instrumentation and Control Engineering

DATE OF BIRTH: APRIL 26 1979

LinkedIn Profile ID:

https://www.linkedin.com/in/avnish-niranjan-jani-yagnik-bhardwaj-6071891-jani-yagnik-bhardwaj-6071891

Resume Link (Click to View and Download)

https://docs.google.com/document/d/1jKkN3jI0bosS2n5_kRWDKG8hPsoiapGu/edit?usp=sharing&ouid=105732122232465720509&rtpof=true&sd=true

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