Engineering Data

CURRICULUM VITAE

To get a challenging career in software industry, implement my ideas and thoughts for the Success and growth of the organization. Achieve organizational goals to grow to higher positions.

B.Tech Electronics and Communication Engineering from Andhra Engineering College, Nellore with an aggregate of 76.0% under Jawaharlal Technological University Ananthapuram in 2019.

Intermediate from Sree Chaitanya Jr College, Nellore with an aggregate of 92.6% under Board of Intermediate, AP in 2015.

S.S.C from Priyadarsini high School, Nellore with an aggregate of 92.0% under Board of Secondary Education, AP in 2013.

Programming Languages

C and C++

Trainings

Embedded Systems at Vector India Chennai.

Programmable Logic controller (PLC) from Siemens.

Operating Systems

Windows, Linux

Title : Performance Analysis of a PPA for Data Path VLSI Design.

Team size : 4 members

Role : Coding and Testing.

Duration : 3 Months

Technologies : VLSI using XILINX ISE 14.7

Description:

All modern processor, including microprocessor, digital signal processor contain Arithmetic Logic Unit (ALU). The computing efficiency of these modern processor mainly depended on efficiency of ALU. An adder is the basic building block for an ALU which performs arithmetic as well as logic operations. The adders like half adder, full adder, ripple carry adder, carry skip adder and carry lookahead adders cannot meet the expected optimization goals, so Parallel prefix adder (PPA) like Sklansky adder, Kogge-Stone adder, Brent-Kung adder and Ladner-Fischer adder. Parallel prefix adder [PPA] are kind of adder that uses prefix operation in order to do efficient addition. These adders are suited for binary addition with wide word. The Parallel prefix adders are derived from the carry look ahead adder. The performance analysis of PPA considered on area, delay and power consumption and simulation are carried out for 8 bit input data width.

ROJECTS UNDERTAKEN

Academic topper in 2017-18 & 2018-19 in university examinations conducted by JNTUA.

I Stood school second place in SSC examinations.

I got 1st prize in poster presentation.

Name : Ch. Srinivasulu

Father’s Name : Ch. Venkateswarlu

Date of Birth : 20th August 1998

Gender : Male

Languages Known : English & Telugu

I hereby declare that the information furnished above is true to the best of my knowledge.

Date: Signature

Place: (CH.SRINIVASULU)

CHAVADAM SRINIVASULU Mobile No : +91-994*******

No:142A, 4th Main Road, Email-ID : **********************@*****.***

Krishna Nagar, Perumbakkam,chennai.

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OBJECTIVE

ACADEMIC QUALIFICATIONS

TECHNICAL SKILLS

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