Engineering Design

SAI SRINIVASA HARANADH BABA SINGAMSETTI

********@*******.*** www.linkedin.com/in/baba-haranadh-524556123/ 716-***-****

EDUCATION

University at Buffalo, State University of New York, Buffalo, NY (expected) Feb 2021

Master of Science in Electrical Engineering CGPA: 3.91/4 Pondicherry Engineering College, India May 2019

Bachelor of Technology in Electronics and Communication Engineering CGPA: 3.20/4

COURSES

Fundamentals of modern VLSI, Introduction to VLSI, Photonic devices, RF and Microwave design, Introduction to VLSI,

Analog circuits, Computer architecture, Programmable Networks, Big Data Analytics, Digital mixed signal design.

ACADEMIC PROJECTS

Electronic Lock on BASYS3 board Basys3 VHDL Xilinx

Designed an Electronic lock which locks automatically after three wrong attempts which resets after specific time, each result is displayed by LED display interface.

Different push buttons on Basys3 used to store passwords. Switches on Basys3 used for entering the passwords.

Password should be entered within 30 seconds from the first digit entered else it resets automatically.

Dynamic Reconfigurable TCAM with Multimode Cadence Virtuoso ADE Spectre

Designed a dynamic reconfigurable TCAM of low power processing chip which is achieved by pipelining.

Tailored self-power generating NOR based TCAM and NAND based TCAM and successfully verified their operation. Conducted a multimode operation for dynamic and reconfigurability.

Implemented whole design on 90X90 um pad frame and verified LVS and DRC of layout which can further processed for fabrication.

1-1 Mash Delta Sigma Modulator with Out of Band-Noise rejection MATLAB

Designed a first order delta sigma modulator using transfer functions and performed fft analysis.

Designed a digital FIR low pass filter using convolution and plotted the zeros of filter on Z-plane

Implemented 1-1 mash delta sigma modulator using first order modulator designed and applied the output to a digital filter designed for out of band noise rejection.

Designed a directional coupler with 20 dB coupling at 3 GHz ADS

Designed a 3- section parallel directional coupler, desired specifications are achieved using capacitors & inductors.

Tailored a layout for the circuit on micro-strip line and able to match the specifications. Implemented the whole design which can be fabricated on the Ruggers RT board.

Big Data Analytics and Image Recognition Algorithms Python

Implemented perceptron, SVM, K-NN, linear and logistic regression, K means algorithms from scratch on MNIST data set and also implemented basic Q learning, double Q learning and SARSA.

Two Stage Amplifier Design with Ahuja Compensation

Designed an Ahuja compensated 2 stage op-amp to overcome the performance drawbacks of single stage amplifier.

The resulting op-amp design had a gain of 60 dB, power requirement less than 1mW with BW 100MHz.

Hardware Implementation of Feature Extraction using Verilog Modelsim

Implementing a Verilog code for feature extraction consisting of 14 features and comparing those results with model developed using MATLAB.

The different features implemented are mean, median, standard deviation, maximum &Minimum value etc

SKILLS

Hardware Languages: Verilog, VHDL, system Verilog.

Programming Languages: C, C++, Python, MATLAB, PERL, TCL, Linux.

Tools: Cadence, ADS, Multisim, NS2, Xilinx, GNU radio.

Hands on tools : FPGA, VNA analyser, Arduino, Raspberry pi, TCP/IP.

Additional knowledge: STA, clock tree synthesis, ASIC, submicron CMOS, RTL analysis.

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