Engineering Engineer

CURRICULUM VITAE

Mail-ID:

****.********@*****.***

K THIRUPATHI É: +984*******

OBJECTIVE: -

To seek a challenging positions where I can effectively put into use my skills and grow professionally there by add value to the organization.

EDUCATIONAL QUALIFICATION: -

M.Tech in Digital Systems and Computer Electronics from Vaagdevi College of Engineering Warangal, (JNTUH), passed in 2010 with First Class.(66%)

B.E in Electronics & Communication Engineering from MVSR Engineering college, Osmania University, Hyderabad, passed with Second Class.(59%)

Diploma in ECE from Govt. Polytechnic College, Warangal passed in 1996 with First Class.(69%)

SSC from Z.P.S.S, Upparapally, passed in 1990 with Second Class.(55%)

EXPERIENCE:12 years

Working as Asst.prof in VAAGDEVI COLLEGE OF ENGINEERING Warangal from june 2008 to till date

SUBJECTS HANDILED:

·Linear digital integrated circuits.

·Switching theory and logic design

·Control systems

·Pulse and Digital Circuits.

·Digital Signal Processing

·Digital logic design

·Electronics devices and circuits

·Voice over internet protocol

·Signals and Systems.

·Ad-hoc wireless sensor networks

LABS HANDILED:

·MAT Lab (Basic Simulation Lab & Dsp Lab).

·Electronics devices and circuits lab

·IC & PDC Lab

·ECA(Hardware & Simulation Lab ( Multisim software ) )

·Analog communications Lab

·Digital communications Lab

OTHER RELEVANT INFORMATION:

Qualified in Faculty eligibility test FET- 2011 JNTU Hyderabad

Worked as a class teacher & Subject co ordinator, NBA team member,

I have got 8th rank in PG-SET 2007, which is conducted by JNTUH

PAPERS/WORKSHOPS:

1) participated in the International journal of innovative Research in Technology paper title is LOW COMPLEXITY WAVELET BASED CHANNEL ESTIMATIO WITH LOW LEAKAGE FOR OFDM SYSTEMS publication in e-journal . Volume-3 Issue-8 January 2017

2) participated in International journal for Innovative Engineering and management Research and the paper entitled Implementation of Dual Modulus Prescalar in True Single Phase Clock(TSPC) in the organizing committee of the Global publication Volume-01 Issue-02 November 2016

3) participated in International journal of electrical electronics and communication ISSN-2048- 1069,paper title is Different selection rules approach for interference cancellation in MIMO Volume:08 Issue:17 Dec-2014

4) participated in the international journal of VLSIsystem design communication systems paper title is 32- bit unsigned multiplier designed by CSLA,CLAA,CBLA adders, Organising committee SEMER GROUPS at hyderabad india during November 2014 SG:IJVDCSV02IS10P3343-2

5) participated in the International journal of Professional Engineering Studies(IJPRES) paper title is An sui channel based multi user interference suppression for UWB system Volume-5 Issue-2 July 2015

6) participated in International conference on electronics communications and VLSI circuits(ICECV-2015) paper title is Proposed encoding Scheme for Reduction energy consumption in network on chip for conference publication

LIST OF WORKSHOPS:

1) work shop on SDP hands on digital signal processing tools algorithms and architectures conducted by jayamukhi institute of technological sciences narsampet Warangal 7thto 19th December 2009.

2)one week work shop on VLSI & embedded systems conducted by vaagdevi engineering college, during 13th to 20th September 2011.

3) participated in two week work shop on computer programming conducted by Indian institute of technology Bombay from May 20th 2014 to june 21 st 2014

PERSONAL PROFILE

Name : THIRUPATHI

Date of birth : 06-08-1974

Marital Status : Married.

Nationality : Indian.

Languages Known : English, Hindi,& Telugu.

Contact Address :

H.No.5-11-438

Premnagar colony, naimnagar

Hanamkonda, Warangal,

Strengths : Bold & Confident,

Skill, Quick Learner, Willingness to Explore

Active Listener

KONREDDY .THIRUPATHI

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