Arun Raja Manjini

adijyi@r.postjobfree.com 361-***-**** Kingsville, TX-78363 linkedin.com/in/arunrjm/ github.com/aaronrjmanj EDUCATION

M.S., in Electrical Engineering Texas A&M University, TX, US Aug 2019 – May 2021 GPA: 4/4 B.Tech., in Electronics & Communication Pondicherry University, India Aug 2014 – May 2018 GPA: 3.5/4 TECH SKILLS

Hardware Description & Verification Languages/Programming: Verilog, System Verilog, C, C++, Perl Bus Protocols: AMBA APB, AXI, SPI Cache Protocols: MESI, MOESI EDA/CAD Tools: Mentor QuestaSim, Synopsys VCS, Xilinx ISE, Spice, Pycharm Text-editor: GVIM Skills: ASIC/SoC design flow, digital design, RTL coding, functional verification, assertion based verification and functional coverage, directed /constraint random verification, knowledge on UVM, computer architecture and micro-architecture.

EXPERIENCE

Assistant System Engineer, Tata Consultancy Services Ltd., India Sep 2018 – Aug 2019

Developed and tested python scripts to detect configuration changes in the device (cisco switch/router) and automated the steps associated it for periodic monitoring, updating and documentation.

Tools and Tech: Networking, PyCharm, Putty, FTP server, Agile PROJECTS

AXI 3.0 bus protocol VIP functional verification using System Verilog

Understanding the design specification and operation of AXI.

Developed a layered test bench to perform full functional verification of AXI protocol which various test cases.

Customized assertions, covergroups and coverpoints with the help of various System Verilog constructs to achieve functional and code coverage using random and directed test cases. Asynchronous FIFO RTL coding

Designed an 8x16 entry asynchronous First In First Out buffer for data transfers which runs on different clocks.

Implemented logic to design a memory with write, read, empty and full conditions.

Used Verilog HDL (RTL development) to establish the FIFO behaviour. Cache coherency problem – Computer Architecture

Submitted a report on overcoming the cache memory coherency problem raised in the multicore processor due to sharing of writable data

Understood how MESI protocol is used to avoid cache coherency. Interrupt controller module design using Verilog

The Verilog RTL design of block level modules interfaces the processor and peripheral slave interrupts which needs to be serviced by the processor with random priority or FIFO priority.

The processor is accessed using APB protocol and interrupts are serviced by the processor. AHB bus protocol functional verification using System Verilog – Universal Verification Methodology (Nov 2020*)

Designed a test plan and Test bench that consisted of active agent (Driver, Monitor, Sequencer), transaction class all connected to DUT via interface.

Generated test cases in accordance with ARM data sheet for triage test failures, functional verification and code coverage.