TEJAS KADALE

San Francisco, CA- ***** Email: adijtg@r.postjobfree.com https://www.linkedin.com/in/tejas-kadale Ph: +1-415-***-**** SUMMARY

I am a hardware enthusiast, looking for Full time Opportunities in RTL Design and Validation. With my skills in Digital Hardware design,I would like to develop innovative products and improve the CMOS technology market. Proficient in : C, Python,Verilog, Assembly, FPGAs, RTL Design and Verification in Verilog, PCB/PCBA design FPGA Tools :Vitis SDK,Xilinx- Vivado, Xilinx -ZYNQ,Virtex FPGA, Arria 10 GX FPGA, Intel Quartus Prime Certificates : Static Timing Analysis Course number : UC -V70TSAML EDUCATION San Francisco State University, California MS in Embedded Electrical and Computer System. 12/2020 University of California, Berkeley, California Cross registration 01/2019 - 05/2019 University of Mumbai India Bachelors in Electronics Engineering . Graduated in 05/2016 Software Skills : C, Python,Verilog, MIPS Assembly,TCL, Pspice, RTL Synthesis and Physical Implementation of ASICs, Static Timing Analysis,Placement, Full Custom CMOS IC design, Post Silicon Validation using FPGAs, IP integration for SOC,CMOS Memory Design(SRAM)

Hardware Skills : Synopsys VCS, Synopsys Design Compiler,Synopsys DVE, Synopsys Custom Compiler, Synopsys HSpice, Synopsys Primetime, Synopsys Formality, Synopsys IC Compiler,Matlab, LTspice, Debugging using Logic Analyzer,CTS,Placement, DFT,Floorplan, Routing, Post layout Timing Analysis, PCB Schematic design, PCB/PCBA layout and Fabrication.

PROFESSIONAL EXPERIENCE Co-op Engineer, GlobalFoundries October 2020- Present RF and mm Wave Test Development : FPGA design using Verilog,C and Python for functional test circuits . RTL design of various interconnects like AXI, SPI, IP integration and Test Architecture development using Vivado and Firmware Development using Vitis SDK. Test and Validate various IC functions by designing custom ATEs with FPGAs Graduate Teaching Assistant, San Francisco State University August 2019 – Present Electric Circuits and Instrumentation Lab : Impart hands on experience to students in various lab equipment, basic electronics circuits and LTSPICE .Perform Simulations for AC analysis, DC Sweep, Transient Analysis, Power calculations Design Engineer, Ashe Controls Private Limited, Mumbai, India March 2017 – January 2018 Succeeded in Designing low noise, high component density Voltage and Current Transducers . Created Embedded System design for various transducer and control panels . Ensured validity various PCB schematics and simulated circuit design in LTSPICE and PSPICE . Worked with various Oscilloscopes, Electrometer, Meggers and Digital Multimeters RESEARCH AND PROJECTS Hardware Validation and characterization of RISC V tape out chip using Arria 10 FPGA and ATE – Present Actively designing the FPGA modules to interface with the tape out of RISCV processor, the results would be compared between Obfuscated and non Obfuscated RISCV core on the same chip and power -performance will be characterized. FPGA modules include Memory IPs, a Program Memory,Data memory, and other vector generation module, input bus controller for Read and Writes and Output validator module and AXI bus written in Verilog. Automated Test vector generation in Verilog and designed automated Python script to generate Intel Memory Initialization files ( .mif ) for loading test vectors. ASIC Implementation of RISC V processor core in Synopsys ICC2 – November 2019 Successfully designed the testbench in Verilog and Assembly for RISC V core .Performed DC Synthesis in Design Compiler,designed Floorplan, performed Automated Placement and Routing of the Chip using Tcl in Synopsys ICC2. Optimized Timing report using ECO in Synopsys Primetime . Total area 25,281 sq um, Frequency 200Mhz. Design of RISC V Processor on FPGA Xilinx ZYNQ - March 2019 – May 2019 Digital RTL design of 32 bit RISC V ISA based Processor on Xilinx ZYNQ . Successfully Designed 3 stage Pipelined Microprocessor design in Verilog. Designed various testbench for individual module blocks like Decoder, ALU, PC and Control Logic in Verilog. Xilinx ZYNQ FPGA based Music Piano - March2019

A FSM design of Music Player described and simulated in Verilog on FPGA . Functions included, button input, pause, rewind, stop and mute.Performed RTL design, testbench development in Verilog and simulation on Xilinx Vivado. PCB Design For Chip Bring-up and testing using ATE - March 2020– April 2020 Designed 4 layer PCB bring up board for validation of the chips using KiCAD. The Board will interface FPGA, Stimulus Generator, Logic Analyser and Power Supply with the Chip to remove encryption, perform DFT and functional Validation. Design of 64x32 bit SRAM using 90nm CMOS Technology September 19 – November 2019 Designed 64x32 SRAM with 6bit address data bus and 32bit input data bus using Synopsys Custom Compiler. Optimised Cell area and Timing by transistor sizing and parametric analysis. Designed custom layout for individual cell module in controller and write driver.

Design and Characterization of Non-Volatile Latch using Resistive Memory Technologies and 28nm CMOS in Synopsys Custom Compiler August 2018 - December 2018

Succeeded in characterising the NV Latch and optimised the area . Also successfully compared ASU ReRAM and Stanford ReRAM model for area and power consumption.