Design Engineering

Girish Chopra

Nashville, TN 973-***-**** **************@*****.*** www.linkedin.com/in/girish-chopra/ https://github.com/grc5

Career Summary

Master’s in electrical engineering with specialization in VLSI Design, to gain knowledge of all aspects of VLSI chip design and apply that knowledge in development of leading-edge products, thereby adding value to the organization I work for. Have explored and gained experience on various EDA tools for two years during the master’s coursework in VLSI, designing CMOS following the RTL2GDS flow. Looking for full-time opportunities in VLSI Design and Verification. Open to relocate anywhere in the US.

Education

MASTERS MAY 2020 NEW JERSEY INSTITUTE OF TECHNOLOGY

· Major: VLSI and Embedded Systems

· Courses: VLSI Design, Semiconductor devices, Embedded Systems, Computer Systems Architecture

BACHELORS JUNE 2015 UNIVERSITY OF MUMBAI

· Major: Electronics and Telecommunication Engineering

Projects

A CDMA BASED NETWORK – ON – CHIP DESIGN

· Designed an energy efficient IC to encode and decode using the Walsh-Like Non-Linear phased code. Wrote RTL for the IC and created test bench for the verification and synthesized it to Verilog files using Leonardo with 90nm TSMC library for implementation

· Developed an ASIC using Mentor Graphic IC Station extracted netlist of the IC using the Verilog. Performed floor planning, cell placement and routing using APR technique and successfully passed the DRC and LVS

· Performed Static Timing Analysis to analyze the set up and hold time to achieve the maximum frequency using Primetime. Used Design Vision to perform the power analysis and optimize the design

CARRY SKIP ADDER

· Designed a 32-bit carry skip adder using CMOS in 180nm TSMC library on Mentor Graphics IC station. Created component library to manipulate the design to get the optimal result

· Used different metal layers for connections, compiled DRC and LVS at the 0.5* lambda to compact the IC. Performed floor planning, placement and routing using PnR technique and pads to complete the IC

· Simulated design on H-spice generated netlist (pex files) and achieved the output at 900 MHz

Experience

VLSI DESIGN INTERN ACEIC DESIGN TECHNOLOGIES JULY ’20 – AUGUST ‘20

· Performed project specification analysis, designed architecture, RTL coding in Verilog HDL and Synthesis

· Designed a SoC based AHB – APB Bridge (AMBA Protocol) design based on specification provided using the AMBA data sheet. Performed a breakdown of the design, understood the timing diagram in the datasheet and then RTL coding using Verilog (Model Sim) was performed on each block (AHB Slave and AHB Controller/ FSM controller)

· Each block was individually synthesized (Quartus) and simulated using the combinational and sequential style of coding and block instantiation was done

· Each instantiated block was combined to form the bridge top. The bridge top is then connected with the AHB master and APB slave

· Successfully debugged and simulated the RTL coding using Model Sim for the write and read operations for different size and burst transfers, complete design is synthesized using Quartus

· Followed the RTL2GDS flow and successfully performed the functions of designing, debugging and verification using the simulation method of the Verilog code for the various size and burst transfer for read and write operation

Technical Skills

· EDA Tools: Mentor Graphics Model Sim, IC Compiler, IC Caliber, IC Station, Leonardo Spectrum, Synopsys Prime Time, Design Vision, Design Compiler, Quartus, Xilinx Vivado

· Protocols: TCP/IP, Physical and MAC Layers for transmission and ARM based AMBA Protocols

· Programming Languages: C++, VHDL, H-Spice, Verilog, TCL scripting, System Verilog, TL-Verilog

· Designing: Schematic designs, Synthesis, Place and route, Timing and power analysis, Pad frame generation, Optimization and Computer Micro-architecture, PCB circuit design

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