Design Engineer Engineering

ABHISHEK B V

*************@*****.*** 914******* www.linkedin.com/in/abhishek-b-v

Experienced in SoC and UVM verification under six months of internship program. In this short period of time able to prove myself as a team player with an excellent track record on completing the project within this stipulated time meet the company expectations and satisfaction through my effective work.

Sion Semiconductor Pvt. Ltd- Intern Apr2020–Nov2020, Bangalore

- Hands on experience in digital circuit design using smartsim.

- Gain Skills in a coding language of verilog, systemverilog, UVM.

- Well known AMBA protocols APB, AHB and AXI.

Teck Genie Solutions– Intern Jul2019–Aug2019, Shravanabelagola

- Hands on experience in Embedded C and Basic python.

- Hands on experience in Arduino, Raspberry PI and Node MCU microcontroller board.

- Skilled with IoT and MQTT protocol.

Programming Languages

Verilog, SystemVerilog, UVM,

Embedded C, MATLAB.

Development Tool

Modelsim, Questasim, Xilinx,

Cadence, Vim, Eagle Cad, LAB

VIEW.

Platform

Linux, windows.

Hands on experience in projects development environment with Design Verification.

Holds hands on experience in project development environment with SoC and UVM Verification.

Holds hands on experience in PCB design of 2-layer and 4-layer Using Eagle Cad and Ki-Cad.

Working experience with a Mentor Graphics Modelsim, Questasim, Xilinx, Cadence, Auto-Desk Eagle Cad and Ki-cad Softwares.

Hands on experience in project development environment with Microcontroller and Microprocessor. B.E in Electronics And Communication - Bahubali College Of Engineering – CGPA – 7.56 Aug2016–Aug2020 PUC in PCMB - BGS PU Science and Commerce - % - 76.67 May2014-Apr2016 SSLC - Loyola High School, Gdenahalli - % - 82.56 Apr2012 – Apr2014 Design and Analysis of Full Adder Using Cadence Virtuoso Platform

Full Adder is a combinational circuit that has an ability to add two bits and a carry input and produces sum bit and carry bit as output. Did this project using CMOS technology; main aim is to reduce the number of transistor required to design one Full Adder it helps to reduce the power loss, area constraint, propagation delay in the chip design. Design and Verification APB Protocol (Advanced Peripheral Bus)

The advanced peripheral bus (APB) is a part of the Advanced Microcontroller Bus Architecture (AMBA) Protocol family it defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity, did this project in verilog, systemverilog and UVM verification. SRAM (Static Random Access Memory) Design and Verification

Static Random –Access Memory is a type of type of Random-Access Memory (RAM) that uses latching circuitry (flip- flop) to store each bit. Done this project in VLSI filed using the coding language as verilog, systemverilog and UVM verification methodology in a design verification platform. IoT Based Home Automation

The IoT based Home Automation will enable the user to use a Home Automation system based on Internet of Things (IoT). The Modern Homes Are Automated through the Internet and the Home Appliances are controlled by using Google Voice Assistance, Adafruit, Control by App, Remote.

Mouth Piece Bot for Patient

It is a communication device useful for the blinds, dumb people, legless or any emergency patient by conveying the messages to respective caretakers.

Smart Irrigation Control Using IoT

As a water supply is becoming scarce I today’s world there is an urgency of adopting smart ways of irrigation. The project describes how irrigation can be handled smartly using IoT. Did this project using thing speak online graphical representation of soil moisture condition.

PCB Design

Done with 2-layers and 4-layers of Arduino Uno, Ic555 Timer, Mobile Signal Detector controller boards PCB Design using Eagle Cad Software.

SoC and UVM Verification Semiconductor

Industry- Sion Semiconductor Pvt. Ltd.

Graphical System Design Platform Lab VIEW - VI-solutions CNC 3D Printing and Design, Laser engraving machine- Indian Institute Of Information Technology Design And Manufacturing, Kancheepuram.

Participated in Assistive Technologies and Divyangjan Conclave & Expo in IISF held at Kolkata-2019.

Participated in DST &Texas instruments India innovation challenge design2019.

Participated in circuitry & robotics event and secured 2nd price in FIESTA-18&19.

Participated in Poster& Paper presentation event in FIESTA-18&19.

Worked as a Coordinator and Vice President in National Level Conference & technical Fest-19 and magazine club at Bahubali college of Engineering.

I hereby, certify that the information stated above is complete and correct to the best of my knowledge and belief. ABHISHEK B V

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