CURRICULUM VITAE
Megha Dewan
W/o Mr. Bharat Dewan House No.-485, Sector-22 Faridabad (Haryana) Mobile No.-099********
E-mail:*************@*****.***
CAREER OBJECTIVE: -
To offer my diversified skills and experience to the organization that offers a challenging carrier with long term opportunities where my skills and talent will be used to achieve organization’s goals, which in turn enhance my capabilities.
WORK EXPERIENCE: - (9Years)
S. No.
Name of Institute
Designation
Time Period
1.
Aravali college of Engineering and Management, Faridabad
Assistant Prof.
July 2018 to till now
2.
DAV CENTENERY COLLEGE,
Faridabad
Visiting Prof.
Jan 2017 to July 2018
3.
D.C.T.M. Palwal
Assistant Prof.
July 2011-May 2015
4.
SONY INDIA PVT. LTD. Delhi
Technical Assistant
Sep 2010 to July 2011
Specialization in VHDL, VLSI (simulation, synthesis and burning on FPGA and CPLD) and Digital Electronics.
Knowledge of Sony products i.e. Sony BRAVIA, Handy cam, Cyber shot, VAIO, Home Theater and Multiproduct) including supplied software support, troubleshooting, connectivity, presale support, editing and settings related issues in products.
Knowledge of system software. Talisma, Avaya, SAP
NTA NET DEC-2018 Qualified
S.
No.
Qualification
Name of the Institute
University
Year
% marks
1.
Master of Technology (M.Tech.-ECE)
D.C.T.M. Palwal
Maharshi Dayanand University, Rohtak
2013
82%
2.
Bachelor of Engineering (B.E.-ECE)
L.I.M.A.T. Faridabad
Maharshi Dayanand University, Rohtak
2010
76%
3.
Diploma (ECE)
G.P.W. Faridabad
S.B.T.E. Faridabad
2007
78%
EDUCATIONAL QUALIFICATION: -
S. No.
Qualification
Name of the Institute
Board
Year
% marks
1.
Senior Secondary (12th)
Govt. Sr. Sec.School, Karnal
Haryana Board
2004
75%
2.
Secondary (10th)
Govt. Sr. Sec.School, Karnal
Haryana Board
2002
72%
COMPUTER PROFICIENCY:
Hardware: Microcontrollers (8051), Microprocessor (8085, 8086)
Software Packages: MS Office (Word, Power Point, Excel), Xilinx 13.1
Languages: BASIC C, C++, Assembly language, HTML, VHDL, Matlab, Tannernew
SUBJECTS UNDERTAKEN:-M.Tech.-VLSI, ICT, Digital Signal Processing
B.Tech Engineering- - Digital System Design, VLSI, Digital signal processing, Digital Electronics, Basics of Electronics, Data Communication, Digital Signal Processing, Communication Engineering and Electronics measurement and instrumentation
B.C.A- Logical Organization of Computer
LAB DEVELOPED:-
VLSI Lab of M.Tech. 3rd Semester, B.Tech.-VHDL Lab, DSP Lab, DE.lab, BOE lab
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CONFERENCE/ SEMINAR/WORKSHOP ATTENDED:-
1.Attended Two Days National Conference on “Signal Processing and Communication Technology” (NCSPCT-13) at Delhi College of Technology and Management, Palwal in May 2013.
2.Attended International Conference on Recent Trends in Electronics Communication & VLSI( ICRTECV-2013) at Al-Falah School of Engineering & Technology Faridabad in July 2013
3.Participated in a workshop at VHDL Designing: DCTM Palwal in July 2013.
PAPER PUBLISHED/PRESENTED:-
1.“VLSI Hardware Design of Generic MIMO Controller with Application in Satellite Orbit Control” in International Journal of Computational Engineering and Management (IJCEM), ISSN (Online): 2230-7893
2.“A Novel Zone Based Auto Speed Control Vehicle Using Infra-Red Encoder” in National conference (NIET, Greater Noida)
3.“Two phase Adiabatic Static Clocked Logic for Charge Recovery” in International conference ICRTECV-2013.
4.“A PID based MIMO controller for space application” in National conference NCSPCT-13
5.“A Serial Communication using Universal Asynchronous Receiver Transmitter” in International conference ICRTECV-2013.
AWARD/SCHLORSHIP:-
1.4th Rank in MDU in M.Tech. 2nd Sem.
2.Received Best Faculty Award-2014, at DCTM, Palwal.
3.Received 2nd prize in Rangoli competition.
HOBBIES: -
Cooking, Listening Music.
STRENGTH: -
Dedication to work, Quick Learner
PERSONAL PROFILE: -
Father’s Name : Mr. Prem Kumar Mother’s Name : Mrs. Satya Devi Date of Birth : 16/01/1987
Language : English and Hindi
Marital Status : Married
Gender : Female
Nationality : Indian
Date: -
Place: - Faridabad
(MEGHA DEWAN)