Sign in

Digital Design and Verification - ASIC, Verilog, SystemVerilog, UVM

Chesterfield, MO
May 16, 2020

Contact this candidate



***** ********* **, ************, ** 63017 E-mail: Ph: 585-***-**** Objective: Actively looking for fulltime opportunities in Digital Design and Verification starting July 2020. Academic Qualifications:

• Rochester Institute of Technology, Master of Science, Electrical Engineering, May 2020 (Expected) Courses: System Verification, Advance Topics of Digital System Design, Design of Computer Systems, Real-Time Embedded Sys.

• University of Mumbai, Bachelor of Engineering, Electronics & Telecommunication Engineering May 2016 Courses: Analog & Digital Electronics, Signals & Systems, Analog & Digital Communication, Microprocessors & Controllers Technical skills:

• EDA Tools: Cadence Virtuoso, NC-Verilog, Synopsys DCS & Primetime, Cadence Spectre, ModelSim, Eagle, KiCAD, LTSpice

• Programming Languages: Verilog HDL, System Verilog, UVM, Perl, Python, Assembly, C, MATLAB

• Misc: Altera Quartus prime, STM32L4 ARM Cortex-M4, PSoC4, Atmega32u4, Keil, Logic Analyzer, Oscilloscope, Computer Arch. Work Experience:

• Hardware Designer – Alstom Signaling, NY June – Aug 2019

− Conducted following tests on magnetics and variety of core materials: Voltage Ratio, Impedance, Inductance, DCR, Dielectric Strength, Resonance Frequency, Construction Quality Inspection, Environmental test (Temperature and Humidity)

− Created and reviewed Component on Specification documents by compiling Bill of Materials, Assembly sheets and test reports

• Hardware Security Researcher – Payatu Software Labs LLP, Pune July 2016 - March 2018

− Custom design, Schematic capture, PCB layout design, soldered and characterized Target Board for hardware hacking which can communicate protocols like SPI, I2C, UART, and JTAG with different peripheral interfaces

− Designed a FTDI 2232h based communication tool to read SPI, I2C and UART protocols using Expliot - Internet of Things Exploitation framework ( (

− Reverse Engineered Philips Health Watch and extracted data from Spansion memory chip. Extracted the firmware and exploited the hardware of the watch with various tools. Worked with and managed suppliers/manufacturing partners in India Projects:

• Ethernet MAC verification using UVM Jan – April 2020

− Verify Ethernet MAC 10/100 Mbps using UVM Methodology. Established testing environment for the DUT by including PHY. BFM includes tasks to set, reset and configure the registers using Wishbone communication. Tx and Rx clock operated at 2.5 & 25 MHz.

• Verification of RCC block from DTMF Receiver using SystemVerilog and UVM Aug - Dec 2019

− Developed a verification environment using SystemVerilog and UVM to perform functional verification on the RTL and Gate Level Netlist of a Results Character Conversion (RCC) block in a DTMF receiver. Testbench features include DPI, assertions, coverage, mailbox, and an algorithmic reference model coded in SystemVerilog and C.

• Multi-Stage Pipeline Shift Register (Parallel Word Shift Register) using Perl and Python Aug - Dec 2019

− Generation of synthesizable RTL & Testbench of a user configured N-stage shift register using Perl & Python scripting.

• Designed and implemented a 12-bit, 4 stage pipelined RISC processor Aug – Dec 2019

− Designed sequential and pipelined 12- bit Harvard Architecture Microprocessors in Verilog HDL. Designed a custom assembler for Instruction sets using Python. Final design was optimized and implemented on Cyclone IV DE0-Nano FPGA.

• Design of a Multi-Channel ADPCM CODEC Jan - May 2019

− Designed, synthesized and verified core-level RTL database of a Multi-channel ADPCM codec, Wishbone IC interface for ADPCM. Sign-off included Static Timing closure, RTL, and ATPG coverage metrics. Implemented a bit exact C model of ADPCM algorithm to generate test vector and test-bench for verification. Final netlist was approx. 4M gates. Clock Domain Crossing and Synchronization issues were solved.

• Top-Down Design of a Memory Access Bus Arbiter in a DTMF receiver Dec 2018

− Designed an FSM for a memory bus arbiter of a Dual Tone Multi-Frequency (DTMF) receiver in Verilog HDL using Cadence NC Verilog, synthesized using Synopsys Design Compiler and verified at the RTL and gate level.

• Design of Digital Systems ( and Aug - Nov 2018

− Designed 45nm CMOS standard cells using Bottom-Up design approach in Cadence Design Systems IC Custom at the transistor level, with custom layout, characterization of each for delay arcs, Patched DRC and LVS errors and performed Static Timing Analysis (STA).

− Designed a 16-bit Carry Select Adder with 50 boundary scan cells attached for in-circuit test using self-designed standard cell library in the hierarchical design, place & route, and characterization. Installed the resulting test cell into a quarter chip pad frame cell.

• Real Time Embedded System Aug - Dec 2018

− Bare-Metal program on STM32L4 to control Stepper Motors, Ultrasonic sensor, and wrote a timer setup library.

• Low Cost FDM Type 3-D Printer, UG Capstone Project ( June 2015 - April 2016

− Designed and built an FDM - 3D printer by implementing stepper motors to move the nozzle in XY axis and eject molten plastic. Hackathons, Trainings and Workshops:

• MIT, Internet of Things Bootcamp, Mentor at SIHH 2018, Speaker at Maker Fest 2018, EFY 2018, HITB AMS and Null community

• LVPEI-MIT Engineering the Eye 2016 Workshop, India ( June 2016

Contact this candidate