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Engineering Project

Warangal, Telangana, India
September 26, 2019

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Email Id : Mobile No: +918*********

Career Objective:

To work with an organization or a company which would offer a healthy work culture and an excellent cooperative working environment that enhances my skill and knowledge and to serve my organization in best possible way with sheer determination and courage.

Academic Qualification:

Masters of Technology in vlsi design 2019

Chaithanya institution of technology and science 70%

Bachelor degree in Electronics and Communication 2017

Talla Padmavathy College of Engineering with 56.79%

Intermediate 2013

JMJ junior college, with 56%

SSC 2011

Maria Rani high School, with 81.7%

Work Experience/Internship:

Industry Name: SION Semiconductors PVT LTD

Duration: 18th February 2019 to present

Role: SOC verification Intern


Title : SPI

Role : Team member

Field : vlsi

Description : Serial Peripheral Interface is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers,sensors and SD cards.

Academic Project:

1. Title: Google Glass

Role: Team member

Field: Electronics

Description: Google Glass is a wearable, voice-controlled Android device that resembles a pair of eyeglasses and displays information directly in the user's field of vision.

2. Title: High speed linear convolution using vedic mathematics

Role: Team Member

Field: Electronics

Description: This propose system provides a method for calculating the linear convolutionwith the help of vedic algorithms that is easy to learn and perform.

3. Title: Hybrid multiplier using MAC unit

Role: Individual project

Field: vlsi

Description:The MAC unit provides the operations such as high speed multiplication with accumulation.

Technical Competency:

●Programming Languages: C, Verilog HDL

●Tools: Xilinx ISE, VIVADO, Questasim, Multisim 11.0

Personal Skills:

●Good work and Time management.

●Punctuality, hard work and willingness to learn.

●Positive Attitude, Self-Motivated and Optimistic.


●Participated in paper presentation held on 11-04-2017 in TECHATHON-17 at Talla padmavathy college of engineering .

●Participated in Project Expo held on 12-04-2017 in TECHATHON-17 at Talla padmavathy college of engineering.

●Participated in two day seminar of oracle at Vagdevi engineering college.

Personal Details:

Name : S.Soujanya Father’s name : S.Kumaraswamy

Gender : Female

Date of Birth : 30th august,1996

Languages known : English, Hindi& Telugu

Address : H.No #2-29, Peddapendial, Dharmasagar(M),Warangal (D), Telangana



I hereby declare that the above mentioned information is true & correct to the best of my knowledge and I therefore request you to be kind enough to give me an opportunity to serve your esteemed organization.

Date :

Place: Warangal (S.Soujanya)

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