Sales Manager Outside
Resume:
ALI NAZEMI
Aliso Viejo, CA ****6
Phone: 310-***-****
Email: *********@*****.***
OBJECTIVE
A technical leadership position in an established company in analog mixed signal and high speed broadband IC design.
POINTS OF STRENGTH
Over 12 years of experience in analog/mixed signal circuit design with proficiency in the design of high speed PLL(up to 10GHz), SERDES(23Gb/s, 10Gb/s, 2.5Gb/s), very high speed moderate resolution ADC(10GS/s) for wire line applications, high speed DAC, output Drivers, reference generation, Feed Forward Equalizers, AGC, I/O etc.
Lead analog IC design engineer on the top level integration of several generations of test chips and transceivers. Responsible for defining a verification flow and leading a team of chip designers to deliver a first time success.
Responsible for the first CMOS 10Gb/s AFE used in the first 10Gb/s DSP based transceiver.
Extensive lab experience. Responsible for the test plan and characterization of transceivers and various analog blocks.
EXPERIENCE
Broadcom Corporation, Irvine, CA June 2009_Present
Senior Principal analog IC design engineer/ Project Leader
Chip lead for the 10Gb/s ADC based low power Ethernet transceiver project, responsible for top level integration and project management, directly involved in the architecture and design of a 10GS/s 6-bit ADC with 50% power/area improvement over previous generation. Transceiver in production.
Lead engineer on the receiver design for 10.3Gb/s XFI SERDES in 28nm CMOS. Architected the top level and managed 3 engineers. Designed several key blocks.
Responsible for the design of the VGA and the receiver front-end used in the dual 23Gb/s transmitter for 40Gb/s RZ-DQPSK in 40nm CMOS. Chip in production.
ClariPhy Communications, Irvine, CA August 2004_May 2009
A start-up specializing in 10Gb/s, 40Gb/s transceivers over fiber cables. Design of the first CMOS DSP based 10Gb/s transceiver (10GBASE-LRM, SR and OC192)
Principal analog IC design engineer/ Project Leader 2nd engineer hired
Responsible for the design and integration of the top level of 10Gb/s AFE in 90/65/40nm CMOS (product being sold to leading companies).
Designed and architected the 10GS/s 6 bit (36dB SNDR) ADC in 3 generations of CMOS technology (latest power consumption reduced by more than 70%).
Designed key blocks: 10GHz phase interpolator, 7GHz BW AGC (40dB SNDR), clock distribution etc.
Managed the design of 10GHz PLL, Reference generation, 10Gb/s FFE, 10Gb/s output driver, LVDS output drivers, XFI 10Gb/s interface, CMOS pads etc.
Interfaced directly with the lead system architect to define the specifications of various analog blocks.
Lead analog designer in the 40Gb/s DSP based receiver feasibility study.
Responsible for the training and mentorship of 7 entry-level design engineers in the Argentina and Irvine design centers.
Solarflare Communications, Irvine, CA August 2002_ August 2004
A start-up specializing in 10Gb/s transceiver over twisted pair copper wire (10Gbase-T).
Senior design engineer
Responsible for the design of the key analog front-end circuits with challenging specifications that enabled the first 10Gbase-T CMOS (0.18um) transceiver in 2004.
PGA: 500MHz BW, 56dB SNDR.
Track and Hold: 100MS/s, 54dB SNDR.
1.6GHz PLL for clock generation: Design of the entire PLL including the VCO, PFD and charge pump.
Transpectrum, Los Angeles, CA July 2001_July 2002
A start-up founded by Dr. Behzad Razavi in February 2001 specializing in high speed low power optical SERDES (OC192).
Senior design engineer
Responsible for the top level integration of the receiver in 0.13um CMOS (lowest power consumption in 2001).
Responsible for the design and architecture of the 10Gb/s CDR including phase detector, loop filter and VCO. Designed various high speed circuits including the 16 to 1 multiplexer.
Conexant Inc., Newport Beach, CA April 1999_July 2001
Currently part of Mindspeed Technologies span off from Conexant on February 2001 specializing in
Internet infrastructure products.
Member of the mixed signal division
Responsible for the design of several low jitter PLL (clock multipliers) including all the sub-blocks ranging from 600MHz to 10GHz used in various wire line product lines: OC12, OC48, OC192 and T3/E3.
Responsible for the design of high precision low voltage reference generation blocks used in wireless and wire line product lines.
CAD TOOLS & SOFTWARE
Strong working knowledge of SPECTRE, HSPICE, and MDS (HP’s microwave design system).
EDUCATION
University of Paris 6 ‘Pierre et Marie Curie’ Paris, France.
MSEE: “DEA d’electronique” with honors
BSEE: “Maitrise d’electronique”
PUBLICATIONS
O. Agazzi et al, “A 90nm CMOS DSP MLSD Transceiver with integrated AFE for Electronic Dispersion Compensation of Multi-Mode Optical Fibers at 10Gb/s Transmission,” ISSCC, Feb. 2008.
A. Nazemi et al, “ A 10.3Gb/s 6bit Time-Interleaved/Pipelined ADC using Open-Loop Amplifiers and Digital Calibration in 90nm CMOS,” VLSI Circuits, June 2008.
O. Agazzi et al, “A 90nm CMOS DSP MLSD Transceiver with integrated AFE for Electronic Dispersion Compensation of Multi-Mode Optical Fibers at 10Gb/s,” JSSC, Dec. 2008.
D. Cui et al, “A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission,” ISSCC, Feb. 2012
PATENTS
US patent 7808417 (related to ADC)
US patent 8094056 (related to ADC)
Several other patents pending.
ADDITIONAL INFORMATION
References and Salary information can be provided upon request. Fluent in English, French and Persian. Good knowledge of Spanish.
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