MANDEPUDI SARAT

Atlanta, GA

+1-470-***-****

ad383d@r.postjobfree.com

EXPERIENCE SUMMARY:

Overall 14+ years of Experience in the semiconductor industry Complete VLSI Backend Design

Strong in Analog Layout & AMS Designing

Expertise in Physical Design/ Physical Verification AREAS OF EXPERTISE:

Extensive skills in all areas of project life cycle from process flow from scratch to tape out. Involved in High Speed Custom Analog layout designs, Physical Design flow, Strong in Implement Layouts, Floorplan.

Involved in Full chip integration of Analog Layouts Design and did Project delivery,tapeout.

Understanding and implementing the IC Full Chip/Digital/Analog/AMS designing methodologies, technology and techniques, matching, shielding, IR related and RDL routing

Worked on IO Ring, IOs, ADC, PLL’s, FLASH ADC, DAC

Strong Exposure on Sign off runs with Mentor Calibre

Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements

Familiar with Cadence Virtuoso environment and various industry physical verification Drc, Lvs,Ant, Dfm,PERC

Experiences in advanced technology node under 180nm/130nm/90nm/45nm/14nm/10nm/7nm/3nm &FinFET

Proficient in PnR flow from RTL to GDS2 & Sign Off Activities

Expert and accurate error fixing without drc in complex and congestive designs and Strong in all Latest EDA tools

Supported Library/PDK design teams and involved Power Mosfet designs

Led Multiple teams, resource allocation & people management for smooth project delivery

Worked in MNC’s INTEL, AMD, ONSEMI, ALTIS Semiconductors(X-FAB),MoSys Professional Experience Summary:

May2023 – Till date Powermind Solution Inc, USA

Electronic Design Engineer

• Responsible to implementation of designs, and Verification

• Involving in Scripting and Automation activities

• Layout Design and Extraction, all verification Activities DRC,LVS,ANT,ERC,RCX Dec 2017 – Jan2023 Tech Mahindra & Laksh Semiconductor to INTEL, India Sr Physical Design Engineer – Technical Lead

• Responsible to Led the teams like 30,20 members and smooth delivery of Project

• Worked on High-Speed Finfet Analog Layout designs and Power management designs

• Technically involvement of blocks, Sub Systems, Top Level and Sign Off Activities DRC, LVS, ANT

• Trained engineers on Custom fixing without drc and Layout verification Critical fixes to every one

• Involved in PnR Activities from RTL-GDS2 complete process in 10nm, 7nm,3nm technologies

• Responsible Of Custom related fixes, Shielding, manual editing, small logical designs e.t.c

• Involved in Block level Floorplan, Timing Analysis, Synthesis and Physical Verification

• Responsible to flow related fixes, tracking, resource monitoring, interfacing with Client

• Involved in Top level exit process, Density Issues and Complete Sign Off Activities to smooth deliverable Feb 2017 - Dec 2017 Sevitech Systems Pvt Ltd to INTEL,ASK Radio Systems, Bangalore, India Sr Staff Layout Engineer

• Responsible for Complete RF Layout design of Ask Radio Systems – USA, TSMC 40nm Virtuoso XL

• It is Base band Filter Receiver (rxbb) Did Layout Design of different RF Block Layouts like filt_amp (filter), pga_amp (programmable gain amplifier), tia_amp (trans impedance amplifier) blocks and integrated them to Baseband Filter Receiver (rxbb) top level. Did layout of resistor banks, cap banks and decoders with different values

• Worked in Intel 10nm Project Lakefield, Led the team 20 pple Custom Layout Activities and PV Activities 2014 - 2017 Symmid Corporation Ltd Sdn Bhd/ Altis semi(X-fab), Malaysia Sr Staff Layout Engineer

• Involved from Scratch to Full Chip Analog & AMS Layout designs. Worked up to 14nm Finfet Technology

• Multiple Projects and designs like SAR ADC, PLL, Flash ADC, VCO, BG,Level Shifters done in Subsystems

• Led the team, Block allocation to engineers, did Full chip integration and Complete Sign Off Activities

• Did Resistor, capacitor matching, different matching techniques, shielding sensitive signal take care

• Power planning, Floorplan and all Layout Verifications like DRC, LVS, ERC, ANT,QRC, Density done

• IO ring Modifications, placing IO pads bump connections and fixed all

• Tools utilized Cadence Virtuoso XL, GXL and Mentor Calibre to close sign off Nov 2011 – 2014 ON Semiconductors Pvt Ltd, Bangalore, India Specialist in Mask Layout Engineer

• Complete product development from Scratch to Top design, Floorplan, Power planning and Verification

• Responsible to Complete design blocks like wrappers, interfacers, Bandgap, digital Ladder, pfd

• Involved in PLL, VCO designing and modifications and proper Layout techniques, signal flow etc

• RC-Extraction activities and Layout improvements, Deep N well, Sub system integration done properly

• Projects involved in Models, WRND, ROADSTER, TITAN, MAKO_SHARK, W96

• Technology is used ONC25, ONC18 and tools Cadence XL, mentor Calibre Jan 2011-Oct 2011 Sicon Design Technologies (Altran), Bangalore, India VLSI Layout Engineer

• Worked on 45nm,90nm technologies and implemented from scratch block level designs

• Responsible to design Band Gap References, Op Amp, LDO designs and clear verification

• Responsible to clean Density Ant, Drc, Lvs errors of PLL, VCO with on time delivery

• Tools used Cadence Virtuoso L, XL and Mentor Calibre for design and Verifications 2008 - 2010 Varient info Systems Pvt Ltd, Bangalore, India VLSI Engineer

• Responsible to improvements of Layouts and signal shielding activities

• Mapped the cells from Standard cell Library and verified all Layout verifications like DRC, LVS,ANT,QRC

• Responsible to design MUX’s, small Layout designs, digital designs and complete LV activities

• Responsible to implement Current mirror, Diffpair layouts and matching, verification

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Tools:

Layout Design : Cadence Virtuoso GXL,XL, L-Edit, Genoa, and Slam-Editor Schematic Design : ADE-L/XL

PV/LV : Calibre, PVS, Assura and Hyper Verify, ICV PD : ICC1&ICC2, Cadence Encounter and Tanner SPR

SCRIPTING : TCL, Perl basics

CERTIFICATIONS:

Physical Design Engineering from TIIT, which is associated with University of California and Cadence Design System (Oct 2006 to Feb 2007)

ACADEMIA: Masters of Science in Electronics and Communications from Andhra University, India (May 2005)

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