Soc Design Hardware Engineer
Resume:
MUHAMMAD IDREES
EXPERIENCE
• Hardware Engineer Dreambig Semiconductor, Lahore
JAN 2021 – PRESENT
Ethernet VIP integration with Ethernet chiplet.
Developed UVM Sequences to send command
descriptor to PCIE Handler block.
Programmed CXL-AXI bridge using UVM.
Integrated I3C with a CPU configured it as master and slave using UVM and verified register access.
Scoreboard planning and development for DHUB
chiplet
Wrote DHUB Chiplet configuration sequences
NIC400 infrastructure system address map testing and configuration
Coverage collection (line, toggle, fsm) for Ethernet chiplet
Instantiated CXL VIP as Endpoint to perform Link training.
RAL access and testing of multiple peripherals.
Tested ethernet MAC for different speeds and
packet sizes
• Trainee Engineer Lampro Mellon, Lahore
JAN 2020 – SEP 2020
SOC Design and Verification
EDUCATION
BE Electrical Engineering (Electronics)
Bahria University Islamabad, Pakistan.
CGPA: 3.00/4.00
2018
Final Year Project (Bachelors)
“Development of MIL-STD-1553 Data Bus Transceiver on FPGA” Developed MIL-STD-1553 to learn practical hardware modeling using Verilog and verified it behavior using FPGAs.
SKILLS
• Verilog/ System Verilog
• UVM
• AXI & AXI-S
• PCIe
• Coverage collection
• Xprop
• Jira & Confluence
• Git & GitHub
• Synopsys VCS
• Verdi
• Linux
• Technical Writing
WORKSHOPS
• Introductory workshop on ‘LAB View'
at Bahria University
HONORS/ ACHIEVEMENTS
• 3rd Prize Winner Final Year Project.
• Prime Minister’s National ICT
scholarship for Bachelors.
VOLUNTEER WORK
• Math and Urdu teacher at Saya School
Islamabad.
• Social Media Marking with SKZ (NGO).
REFERENCE
M. Awais Karim
Manager Hardware
Dreambig Semiconductor Inc.
*****@************.***
**************@*****.***
https://www.linkedin.com/in/idrees96/
Present: Al-noor Apartments, Jail Rd, Lahore.
Permanent: Chak 34/14.L, Tehsil Chichawatni,
District Sahiwal.
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