RAVI KIRAN MODALI

**** *. ********** *****, *****, AZ-85281• https://www.linkedin.com/in/ravi-kiran-modali-9986159b •480-***-**** • aczglh@r.postjobfree.com

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SUMMARY

Electrical Engineering Graduate student specializing in Digital VLSI Design with a professional experience as Physical Design Engineer, designing standard-cells in 40nm process, looking for full-time position from April 2017 to enhance my strong technical skills and analytical ability in the field of Digital VLSI ASIC/SOC Design Physical design. EDUCATION

Masters of Science in Engineering, Electrical Engineering Aug’14 - Dec ‘16 Arizona State University, Tempe, Arizona

Bachelor of Technology; Electronics and Communication Engineering Aug’12 - May ‘12 SRM University, Tamil Nadu, India

PROFESSIONAL EXPERIENCE:

Physical Design Engineer Intern – Analog Rails, Arizona Oct’15 – Apr’16

Designed standard cell library in 40nm PDK, performing Circuit simulations (rise/fall/delay) using AR-tool kit.

Hercules DRC and LVS used for physical verification & Synopsys StarRC used for parasitic extraction in cadence virtuoso.

Performed Characterization of the cells using liberate tool and generated liberty (.lib) files.

Routed the standard cells to set the pattern to be followed by the automatic placer & router of the EDA tool.

Responsible for writing synthesizable RTL code in Verilog for complete standard cell library. Software Engineering Analyst – Accenture Services Pvt, Ltd. (Client: Bank of America) Aug’12 – Jul’14

Developed test suits and scripts in C for designing the modules and unit testing is performed to check for any breaks in their functionality in Agile – Kanban methodologies.

TECHNICAL SKILLS:

Simulation Tools : Cadence (RTL Compiler, Virtuoso, Encounter, Innovus, Spectre, Caliber), ModelSim-ISE, Synopsys (Hspice, PrimeTime).

Programming Languages & OS : C, Verilog, bash, Perl, Tcl, UNIX Scripting, GIT-Repository, Windows, Linux (Ubuntu).

RESEARCH PROJECTS - ARIZONA STATE UNIVERSITY: Mar’16 – Aug’16 Constrained optimization in Energy and Performance using generalized scaling models (Power and Performance management)

Worked on a Performance model algorithm in C by providing existing Power model as input in the kernel running on android OS on ODROID XU4 (octa core).

Automated different benchmarks run in bash script to analyze different performance counters at specific time intervals and frequencies using a performance tool, PERF.

ACADEMIC PROJECTS: Aug’14 – Dec’16

Design and custom layout/APR of 2KB 6T SRAM based L1-Cache memory in FinFETs (Tools: Cadence 7nm PDK, Cadence-Innovus)

Designed and implemented the physical design of 2KB dual word issue L1-Cache memory on 7nm process PDK.

A custom layout standard cell design of 128 bit decoder is build using cadence virtuoso and pitch-matched the design.

Designed pre-decode and Control logic block using APR tool, cadence Innovus and verified the complete functionality in HSpice with a test-bench by generating waveforms for all the signals at different PVT corners. Dynamic Power Management in Multi-core Architectures: (Tools: ODroid XU4, Low power, performance management)

Simulated benchmarks on ODroid XU4 (octa core) running on Ubuntu, on multi core configurations using bash script.

Collected data for metrics like IPC, temp., Power, execution time, Cache-misses for optimal core configuration. Design of a Convolution and Max-pooling Engine on Image (Tools/Tech: Cadence 32nm PDK, Cadence Encounter) - VLSI Design

Developed RTL code in Verilog, verified in Modelsim-ISE with gate level netlist being synthesized by RC compiler.

Generated the physical design on chip using Cadence Encounter APR tool by floor planning, pin placement, power rails, trail route, Nano route, pre/post clock tree synthesis and performed post layout verification (DRC/LVS) and Timing optimization. Design and custom layout of 32X32 bit Register File array (Tools/Tech: Cadence 32nm PDK, Cadence Virtuoso) - VLSI Design

Implemented the physical design for a custom 32x32 bit Register File using 8T SRAM Cells with one read and one write port.

Designed schematics/layout in cadence virtuoso and performed DRC/LVS and parasitic extraction (.spf) on Post layout.

Complete functionality (read/write) is checked in HSpice by simulating waveforms for all PVT cases. RTL-to-GDSII flow of 2-bit adder using Automated Design Flow techniques (Tools: RC Compiler, Encounter, Primetime) - VLSI

Synthesized design using Cadence RTL-compiler and performed Automatic Placement/route (APR) Using cadence Encounter.

Done floor-planning, pin-placement, power-rails, Nano-route, clock-tree synthesis using TCL script, Power using Primetime. Design of an 8-bit Modulo Adder with Lowest possible Energy Delay Product (Tools: cadence Virtuoso, HSpice) - Digital Design

Designed layout is optimized to achieve low energy- delay product as well as a minimal area using cadence virtuoso schematic/layout editor in cadence-6 with 20.35 pJ-ps as EDP and 183.480 sq.μm as area. RELEVANT COURSE WORK:

Advanced VLSI-Design, VLSI-Design, Computer- Architecture, System level Design for Multicore Architectures, VHDL/Verilog course, Digital Systems and Circuits, Semi-Conductor Memory Technologies & systems, Semiconductor Device Physics.

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