Mark A. Johnson

PO Box ***, Spicewood, Tx. ***** 830-***-**** acxeae@r.postjobfree.com

SUMMARY

Thirty two years experience in ASIC/FPGA architecture, design, simulation, synthesis, documentation,

debug, verification, release and support.. Major strengths in conceptualization, planning,

implementation, release and support of hardware and software. Solo-authored three patents and two

publications. Received Outstanding Technical Achievement Award.

PROFESSIONAL EXPERIENCE

SouthWest Research Institute, San Antonio, TX, FPGA Logic Design (Direct) 2001 - .

Coding/Documenting/Testing designs for SpaceCraft / DoD applications. Using VHDL, Verilog,

ModelSim for Xilinx and Actel FPGAs. Bus architectures include cPCI, SPARC, VME, and 8051.

Coded cPCI core. Serial architectures include CCSDS, HSSDS and RS422 for TeleCommand /

Telemetry spacecraft applications. Worked in conjunction w/ staff at Stanford University, Johns

Hopkins Advanced Physics Lab, and University of Colorado. 25 FPGAs designed, documented,

simulated, synthesized, and tested in the first 6 years.

Cirrus Logic, Austin, TX, ASIC Logic Design (Consultant) 2000 - 2001

Coded design for bus interface in ethernet adapter / set-top box. Used Verilog, VHDL, Synopsys,

QuickBench.

Agere/Lucent, Austin, TX, ASIC Logic Design (Consultant) 1999 - 2000

Coded design for ALU in OC48 Network Processor. Responsible for mapping entire chip design

into Xilinx FPGA. Ran Verplex Formal Verification tool.

Tekmos, Austin, TX, FPGA Logic Design (Consultant) 1999

Coded design for 82380 replacement. Used Verilog and Synopsys for ORCA FPGA.

Bell Labs/Lucent, Holmdel, NJ, ASIC Logic Design (Consultant) 1998 - 1999

Documented and coded design for TeraBit Router chip. Gate count over one million. Used VHDL

and Synopsys.

AMD, Austin, TX, ASIC Verification (Consultant) 1997 - 1998

Coded and maintained hardware test emulator written in C that interfaces to a 486 via JTAG and

Parallel test ports. Wrote test cases and analyzed results. Ran regression suites and analyzed

results. Used Verilog, C, Perl, Silicon Arena.

National Semiconductor, Arlington, TX, ASIC Logic Design (Consultant) 1995 - 1997

Responsible for all phases of definition, design, documentation, simulation, synthesis, timing

analysis and release of several key blocks on a PCI peripheral chip. Two new patents

incorporated into design. Used Verilog and Synopsys. Also wrote bus monitor behaviorals.

IBM. Research Triangle Park, NC, ASIC Logic Design (Direct) 1983 - 1994

Lead designer for bus interface and data management logic on all ASICs used on Token Ring /

EtherNet adapters. Responsible for all phases of definition, design, documentation, simulation,

synthesis, timing analysis, release and support. Consolidated four different bus interfaces in one

ASIC. Advised other design groups in adapting design to other interfaces. Assisted in converting

designs to VHDL. Authored publication and received an Outstanding Technical Achievement

Award.

Originated project / received patent for high speed USART chip incorporating ASYNC, BISYNC

and SDLC serial Data Networking Protocols.

Developed small adapter in VHDL using Xilinx FPGAs.

IBM, Kingston, N.Y, ASIC Logic Design (Direct) 1978 - 1983

Designed and verified a Memory Control card that replaced current effort in IBM 8150.

Implemented DEC with DED/SEC ECC. Authored one publication.

Designed, built and debugged several programmable test adapters to interface with the IBM 8150

during its design phase. Also designed and built hardware emulator for Memory Controller bring -

up.

PROFESSIONAL ACHIEVEMENTS

Patents (Sole Authorship)

"Self Correcting Serial Baud/Bit Alignment" - patent number 5,058,140

"DMA configurable channel with memory width N and with steering logic comprising N

multiplexors, each multiplexor having a single one-byte input and N one-byte outputs" - patent

number 6,065,070

"DMA configurable receive channel with memory width N and with steering logic compressing

N multiplexors" - patent number 6,185,633

Outstanding Technical Achievement Award

"Definition and Implementation of Flexible Token Ring System Interfaces"

Publications

"LSSD Clock Multiplexor" - IBM Technical Disclosure Bulletin Vol.33 No.7

"Symmetric Odd Weight (39/32) DED/SEC Code with Package Error Detection for Four Bits" -

IBM Technical Disclosure Bulletin Vol. 24 No. 11B

EDUCATION

BSEE, University of Vermont, 1978

BSMath, University of Vermont, 1976

JOB SKILLS

Languages

Verilog, VHDL, PLI

C/C++, Perl, Assembler, REXX, PLS, CLIST, CP/CMS Fortran, APL, Basic

Tools

ModelSim, Xilixnx ISE, Actel Libero, Synplicity, Synopsys, QuickBench, Verplex

MSWord, FrameMaker, WordPerfect, Interleaf, TGIF

Hardware

PCI, ISA/EISA, PCMCIA, PowerPC, 68XXX, MicroChannel bus architectures

Sonet/SDH, Token Ring, EtherNet, ATM, ASYNC, BISYNC, SDLC/HDLC protocols

Xilinx/Actel/ORCA FPGAs, DATAIO PROM/PAL programmer, Logic/Protocol Analyzers

Systems

UNIX/AIX, DOS, Windows, OS/2, VM, MVS

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