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Verification Engineer

Location:
San Jose, California, United States
Posted:
October 03, 2016

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Jaini Shah

**** **** *** #***. *** Jose, CA

408-***-****

acwv9c@r.postjobfree.com

OBJECTIVE

ASIC Verification engineer with 4.5 years of experience with ASIC Design Cycle Experience in building verification environment, understanding protocols/specifications, implementing and executing verification strategy.

EDUCATION

Charotar Institute of Technology Gujarat, India

B.E. Electronics and Communication Engineering May’10

GPA-3.5/4.0

SUMMARY

Experience in SystemVerilog/UVM based verification environment development for sub-system.

Experience in defining Test Plan for sub-system level designs.

Experience in creating random, constrained-random and directed Test Cases with varying scenarios.

Experience in defining and writing Functional Coverage and achieving coverage closure.

Have in-depth knowledge of bus protocols like AXI, APB, OCP, SPI and network protocols like Ethernet (10G) and pro-efficiency in debugging RTL.

EXPERIENCE

E-INFOCHIPS, Ahmedabad, India July `13 – March`16

Verification of Customer IP Download Block in SoC used in Automated Test Equipment

The IP was instantiated 17 times which was responsible for writing registers based on the commands provided to the command queue present in the block which is connected to most of the modules in SoC.

Developed Test Plan that covered the basic scenarios as well as the edge case scenarios.

Was responsible for Bring-up testing, test case implementation for the full functionality of the block, worked among the team members to resolve bugs, running regression and debug failures and testbench(developed in TVM – Client specific methodology build around UVM) issues in Weekly regression report and developing Functional Coverage(which came to 99%).

ARM Based SoC Verification

Worked on verifying an ARM based SoC with Env implemented in UVM which had multiple processors and interconnect using OCP/APB protocols connected to other devices and slow peripheral devices like SPI.

Developed SPI Slave UVM Env for Unit level and Sub-system level Verification. Implemented and debugged test cases to verify the path from OCP -> APB -> SPI. Also created tests to verify SPI IP at unit level. Written and tested basic connectivity assertions and functional coverage for SPI.

Maxwell FPGA Verification.

Involved in checking connectivity of particular set of features being reported to the Support Block used in an FPGA. Features involved checking of Error Status, Alarm Status, Busy and Cond.

SIBRIDGE PVT LTD, Ahmedabad, India June `11 – July`13

Verification of Ethernet IP

Involved in implementation of Verification IP of Ethernet Protocol.

Developed test-cases for MAC as well as PHY layer for Ethernet VIP as per the specification of 10G protocol

Involved in developing test-cases and regression management of complete ETHERNET VIP.

Helped develop functional checkers and coverage for interface like 10G for Ethernet

Professional Skills

Languages: System Verilog, Verilog, UVM, basic concepts of C++.

Tools: QuestaSim, IUS, VCS, Eplanner (Test Plan Creation), Emanager(Regression), ClearQuest (Bug Reporting), ClearTool, Simvision (Waveform Debugging).



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