Engineering Project

LAKSHMAMMA K M

kirisave

Channarayapatna taluku

Hassan(Karnataka)-573124

Phone:812-***-****

Email: acwnqo@r.postjobfree.com

Career Objective:

To serve an organization to the best of my knowledge, efforts, ability and carve a career for myself to achieve maximum performance for professional growth and work in a company and grow with the company. Realize my highest potential working as a key player in this challenging and creative environment.

Synopsis:

A fresher with MTECH(80%) in VLSI and embedded systems (Electronics and communication Engineering )from Visvesvaraya Technological University, Belgaum. Expertise in basic knowledge of core subjects.

Professional Summary:

Graduated from Visvesvaraya Technological University with First Class with Distinction.

Excellent in maintaining interpersonal relationship.

Basic knowledge in HDL(Verilog) and Embedded language.

Basic knowledge in Cadence software and VLSI

Flexible attitude to mold into any given situation.

Quick learner and excellent team player having ability to meet tight deadlines and work under pressure.

Good analytical skills, problem solving capabilities and soft spoken.

Hard working and respect for project deadlines.

Educational Qualification:

Completed M. Tech in VLSI and Embedded system, with 80% in P.A college of Engineering Mangalore.(2013-2015)

B. Tech (Electronics and communication Engineering) with aggregate 73% in 2009-2013 from Visvesvaraya Technological University, Belgaum

Experience:

I was working at Decible Inc as trainee software engineer.(3 months)

I had 6 month experience at Sri vidya vinayaka engineering college as a Assistant professor Bangalore .

SKILL SET

Languages

Basic C,8085 assembly language, Microcontroller 8051,HDL(verilog)

Operating System

MS Windows /2007/XP/2008

Computer applications

MS Office, Matlab, Keil,Cadence,Tanner Tool,xilinx,VLSI

Academic Project (during B.E):

Design and implementation of wave-pipeline throughput in Network On chip:

Project Title : Design and implementation of wave-pipeline throughput in Network On chip

Languages : Verilog, VHDL

Environment : Windows 7

Team Size : 4 Members

Duration : 4 months

Role : Design, Develop and Test

Description:As the complexity of systems-on-chips (SOCs) increases, the network-on-chip (NOC) is being adopted as a scalable communication-centric solution for integrating numerous on-chip components.High Guarantee Throughput.NOC is achieve High Bandwidth, and Energy efficiency. This project has presented a practical and cost-effective design of the proposed BW switch to support guaranteed throughput and wave-pipelining features.

Academic Project (during M.Tech):

RTL Design and FPGA Implementation of Canny Edge Detector with Real Time Threshold Adjustment Capability

Project Title : RTL Design and FPGA Implementation of Canny Edge Detector with Real Time Threshold Adjustment Capability

Languages : HDL,MAT lab

Environment : Windows 7

Duration : 6 months

Role : Design, Develop and Test

Description:

Edge detection is the basic operation in image processing and has wide application in research area. Many edge detection algorithms have been proposed such as Robert detector, Prewitt detector, Kirsch detector, Gauss-Laplace detector and Canny edge detector. Edge detection is a very important area in the field of Computer Vision. Edges define the boundaries between regions in an image, which helps with segmentation and object recognition.

Achievements

Participated in all India science Exams during school level.

Participated in many Dance and singing competitions in school.

Participated in state level Technical paper presentation at acharya engineering college at Bangalore.

I have published VLSI related paper in Iinternational journal(IJSR).

Extra-Curricular Activities

Listening to music.

Playing shuttle clock

Dancing.

Reading books.

Personal Details:

Date of Birth : 18/05/1992

Marital Status : Single

Languages Known : English, Hindi and Kannada, Telugu

DECLARATION:

I acknowledge that the above-mentioned information regarding myself is true to the best of my knowledge.

Place: Hassan

Date: (LAKSHMAMMA K M)

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