Engineer Design

Shravanthi Pachalla

**** *** ***** ****** **. #**, San Jose, CA 95130

408-***-**** **********.******@*****.***

https://www.linkedin.com/in/shravanthip

EDUCATION:

M.S., Electrical Engineering

San Jose State University, Fall 2015

SKILLS:

●Algorithm and Data Structure Design, VLSI, ASIC Design

●Programming Languages: Java, Verilog, VHDL

●Tools: Design Compiler, Cadence Virtuoso, ModelSim, Matlab, Xilinx, Altera QuartusII, JIRA

WORK EXPERIENCE:

Engineer, SSR Labs, Pacifica, CA Mar. 16 - Present

Developing openCL and openACC functions for coprocessor.

Graduate Teaching Assistant, San Jose State University, CA Aug. 14 - Jan. 15

●Taught Electric Circuits to undergraduates.

●Included weekly office hours, grading and mentoring.

Software Engineer, Logica, Bangalore, India Jul. 10 - Apr. 13

●Senior engineer in charge of designing and executing verification plans.

●Mentoring junior developers and bringing them up to speed with industry standards.

●Designing of Message Routing and setup of Message Routing Tables for messages of SWIFT format.

●Focus on high volume scalability(5 million messages/day), security of messages, speed and 24/7 reliability.

●Bug Detection & Testing, System Testing, Regression, Integration testing. Test planning and execution.

ACADEMIC PROJECTS:

●Comparative Performance Evaluation of GPU

Designed, analyzed and compared Histogram, Sobel Filter, Stereo-Disparity & Image De-noising on GPUs GEFORCE840M and NVS4200M using CUDA programming.

●Design of 4X4 Keypad Scanner and Encoder

Involved designing of a Keypad Generator- to monitor the various combinations of keys pressed depending on the column and row combination FIFO- to store the data coming from the Keypad generator, Decoder- decodes the binary data coming from FIFO into decimal format, Controller- controls the functioning of all the other modules, by sending and receiving appropriate signals.

The verilog code was simulated and synthesized using Design Compiler. Also static and dynamic timing analysis was performed

●Design, Simulation and Synthesis of Spread Spectrum Search Engine

The design detects the frequency and phase of a direct sequence PSK spread spectrum signal mixed with several other spread spectrum signals below the noise floor.

Designed and implemented 32 correlators for the receiver each having a 5-staged pipeline and operating at 200MHz frequency.

The design was simulated and synthesized using Synopsys VCS and NC Verilog

●Design and implementation of a 32-bit, 5 stage pipelined processor

Designed a 5-stage pipelined MIPS Processor with a Data path and Control path for single cycle CPU.

The design supports for store word,load word, jump,R-type and branch instructions. The design was simulated using ALTERA ModelSim

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