Verilog, VHDL,System verilog,perl

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MANOJ KUMAR

Contact No: +91-945*******

Email id: *****.********@*****.***

CAREER OBJECTIVE

To obtain a creative and challenging position in an organization that gives me an opportunity for self improvement and leadership, while contributing to the symbolic growth of the organization with my technical skills. ACADEMIC QUALIFICATIONS

Class Year Board/

University

Institute Marks Post Graduate

Diploma in VLSI

Design

(PG-DVLSI)

2016 CDAC CDAC-NOIDA passed

B. Tech (ECE) 2011-2015 JNTU-HYD Mallareddy Institute of Technology & Science

70.2

XII 2011 IPE Gouthami Junior College 95.7

X 2009 SSC Chaithanya Bharathi High

School

90.1

SKILL SET

Experience of RTL coding in Verilog and Vhdl

Knowledge of Basic System Verilog

Strong in Simulation and debugging skills

Familiar with ModelSim (Mentor Graphics), Questasim simulation tools

Good understanding of Digital Fundamentals

Exposure of synthesis

Strong in documentation and presentation skills

Good Communication skill and ability to work in a team environment TECHNICAL PROFICIENCES

Frontend tools : XILINX ISE, Modelsim PE 10.4a, Presicion RTL plus

Backend tools : Calibre pyxis schematics and Layouts

Programming Languages : C&C++ Basics, VERILOG,VHDL, PERL

MS Office Tools : MS-Word, MS-PowerPoint, MS-Excel PROJECT PROFILE 1

Organization : CDAC-NOIDA

Title : Simulation and Synthesis for i2c bus controller using verilog HDL Duration : 2 months

2

Team size : 2

Role Played : Developer and Tester

Skills used : Verilog HDL

Description : The Inter Integrated Circuit Bus or I2C bus is a synchronous serial data link that operates in half duplex mode. Here I2C master bus controller using a field programmable gate array(FPGA). It is interfaced with a memory, which acts as a slave. The main aim of this project is to enable faster device to communicate with slower devices without any data loss. Advantages of this project is it requires only two signal lines sda and scl, flexible data transmission rates, devices have a simple Master/Slave relationship, each device on the bus is independently addressable. This module was written in verilog HDL, simulated and synthesized by using Modelsim PE 10.4a and Precision RTL tools. PROJECT PROFILE 2

Organization : Mallareddy institute of technology & science Title : A Spurious Power Suppression Technique for a Low Power Multiplier. Duration : 2 months

Team Size : 3

Role Played : Team leader, Developer.

Skills used : Verilog HDL

Description : The main aim of the project is to suppress unwanted power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. PROJECT PROFILE 2

Title : Electrical Equipment Control Using PC

Duration : 1 month

Description : The main aim of this project is to control all electrical equipments like home appliances through PC by using a micro controller and relay. The advantage of this project is less time consuming process.

EXTRA CURRICULAR ACTIVITIES

Robotics: Attended a two day ARK Techno solutions workshop at MRITS, Hyderabad, where we have sessions on various robots like line follower, obstacle follower and obstacle avoid using multipurpose optical sensors and sound sensors using Arduino tool.

Basic Electronics Hardware design: Attended a two day Physitech Electronics workshop at MRITS, Hyderabad, which involved the design, development, construction and testing of an electronic product.

Participated as a volunteer in FURKETZ 2K12 A National Level Fest held in college. 3

PERSONAL PROFILE

Name : CH.Manoj Kumar

Father’s Name : CH.Shankaraiah

Date of birth : 07-07-1994

Marital Status : Single

Nationality : Indian

Locality : Hyderabad

Hobbies : Cooking, Listening songs, Doing exercise, Watching wwe Passport holder : Yes

Languages known : Telugu, English, Hindi

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge. If given an opportunity I would perform up to the best of your expectations. Place: Hyderabad yours sincerely

Manoj Kumar

Date:

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