Mobile: +917*********

Email: actnnr@r.postjobfree.com

SAINATH BHAMIDIPATI

CAREER OBJECTIVE:

I am willing to pursue a career in Electronic industry, where opportunities exist for innovation, knowledge enhancement, and professional growth and to utilize my technical skills to the best possible benefit of the organization I serve.

ACADEMIC QUALIFICATION:

Have successfully completed M.Sc. electronics(specialization in VLSI) under Andhra University, Visakhapatnam in the year 2013 with a 89% (Andhra University 1st rank)

Have successfully completed B.Sc. electronics under Hima sekhar degree college, Andhra University, Visakhapatnam in the year 2011 with a 80%

Have successfully completed Intermediate(M.P.C) under Saikulwanth Junior College, Board Of Intermediate Education, Hyderabad in the year 2008 with a 87.3%

Have successfully completed S.S.C under City Public School, Board Of Secondary Education in the year 2006 with a 78%

WORK EXPERIENCE:

WORKING AS MANAGER PURCHASE & RF ENGINEER IN ANDHRA ELECTRONICS LIMITED FROM 2014 FEB. TILL DATE.

CORE SKILLS:

Working knowledge in Filters(LC,CRYSTAL,CAVITY)

GOOD WORKING KNOWLEDGE IN PURCHASE OPERATIONS.

DESIGINING OF CAVITY FILTERS USING HFSS

Good Understanding in Digital design architectures and RTL coding

Good understanding of Cadence Virtuoso tool.

Good knowledge of FPGA Design Flow

Hardware design using Verilog.

Knowledge in System Verilog.

Knowledge in Synthesis and Static Timing Analysis.

Digital Design, FSM,CMOS Circuits.

Experience in CADENCE EDA tools like: NCVerilog, NCSim, SimVision, RTL Compiler.

AREA of INTEREST:

Circuit Designing and VLSI.

Programming in VERILOG.

PROJECT & TRAINING:

ASIC VERIFICATION PROJECTS:

MINI PROJECT:

Sequential Multiplier Design

Msc ACADEMIC PROJECT:

Project on Implementation of UART.

An UART is responsible for performing the main task in serial communications with computers.components such as laptops keyboards and modems are few examples of devices that employ UART circuits.

The main aim of this project is to implement the UART design using the Xilinx ISE 13.3I tool.

TRAINING:

Post Diploma in VLSI Design at Indian Institute of VLSI Design and Training in Bangalore with a period from June 2013- January 2014.

PERSONAL STRENGTHS:

Leadership and Growth Potential.

Hard working and Adaptability.

Willingness to learn & develop.

PERSONAL DETAILS:

Father’s Name : BHAMIDIPATI RAVI SHANKAR

Date of Birth : 18th June 1991

Gender : Male

Nationality : Indian

Marital Status : Single

Languages Known : Telugu, English, Hindi

Hobbies & Interests : Organizing Events & Activities, Making Friends, Cooking, Reading Novels, Playing

Cricket as a fast bowler.

Communication address : C/o BH V S RAMAKRISHNA, 102, parijatha Nilayam, Phanigiri Colony,

Chaithanyapuri, Dilsukhnagar, Hyderabad

Permanent Address : S/o Bh. Ravi Shankar, D.No. 7-9-16/1/, Besides Hanuman Temple,

Mallimadugulavari Veedhi, Anakapalli - 531001, Visakhapatnam Dist. AP.

DECLARATION:

I do hereby declare that all the particulars made above are true to the best of my knowledge and belief.

Date :

Place : VISAKHAPATNAM

(SAINATH B H)

Contact this candidate