Design High School

RESUME

GOPALAKRISHNAN.E

Room No:***,

Munusamy Building,

Royal Cardiniya Comfort Suite, Email : ************@*****.***

Bommasandra, Bangalore. Mobile : +91-812*******.

CAREER OBJECTIVE:

To work for a reputed firm in specialized areas related to VLSI Design, with significant knowledge of Design For Test, who is eager to learn new skills and meet new challenges. Self directed team player who adds both practical and organizational insight to his team. Excellent presentation skills with extensive classroom teaching and demo experience.

SUMMERY:

Having 2 Year 6 Months of experience in Verilog based Design and Verification Environment, Bangalore.

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

Experience in using industry standard EDA tools for the front-end design and verification

EDA TOOLS EXPERIENCE:

Tools : Questa Sim, Xilinx, Altera Quartus II, Modelsim.

TECHNICAL SKILLS:

Languages: C, Verilog, SystemVerilog.

Operating Systems: Windows

Digital electronics, ASICs, FPGA.

PAPER PUBLICATION:

“FPGA implementation of Robust Audio Watermarking for Real Time Copyright Protection” in proceeding of IEEE Computer Society has been accepted and it is to be published IEEE Xplore.

PROJECTS:

Front-End Design and Verification of small ASIC based designs using Verilog and System Verilog in ModelSim, Questa Sim Tools:

Dual Port RAM - verification

HVL: System Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

RTL coding of small building blocks of ASICs such as memory controller, FIFO etc. in ModelSim/ Questa Sim using Verilog and synthesizing the codes to gate-level netlist using Xilinx tool, used as the DUTs for implementing Verification methodologies and verifying the designs using Layered test benches in System Verilog and an introduction to UVM.

An Experimental Implementation of Convolution Encoder and Viterbi Decoder by FPGA Emulation

FPGA Implementation of Robust Audio Watermarking for Copyright Protection and Data Hiding.

EDUCATIONAL QUALIFICATION:

ME VLSI Design from Anna University Chennai-25, Regional Centre, Coimbatore-47, and Under Anna University Chennai with 7.5 CGPA passed out July 2013.

BE Electronics and Communications Engineering from Anna University Chennai with 69% passed out May 2011.

HSC from Government Higher secondary school, Under State board of Tamilnadu with 69% passed out April 2007.

SSLC from Government High school, Under State board of Tamilnadu with 71% passed out April 2005.

AREAS OF INTEREST:

Digital design, ASIC Design, FPGA Implementation, RTL Design & Verification

PERSONAL PROFILE:

Date of Birth

: 14-05-1990

Sex

: Male

Languages Known

: English

Nationality

: Indian.

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place : Bangalore

Date :

GOPALAKRISHNAN.E

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