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Design Engineer Assistant

Location:
Bengaluru, KA, 560078, India
Posted:
February 15, 2016

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Resume:

BELLAMKONDA SRINIVASARAO

Address: #**/*, ********** ******, **** cross, 24th Main Phone: + (91-740*******. 6th Phase, JP Nagar, Bangalore-560078. Email: acti7y@r.postjobfree.com. OBJECTIVE

Seeking a position as Physical design engineer with provision for innovation and creativity with candid and cooperative work culture that fastens the growth of the company. PROFESSIONAL STRENGTHS

Good foundation of semiconductor device physics.

Knowledge of Physical Design flow (RTL to GDSII).

Strong commitment to professional development and eager to learn, expand knowledge and capabilities.

Hard working, enthusiastic, innovative and thinking out-of-the-box attitude.

Strong organizing, verbal and written communication skills.

Ability to work as part of a team as well as independently. TECHNICAL SKILLS

Cadence SOC Encounter, Schematic editor, Virtuoso layout editor and SpectreS.

Programming languages: C, C++, VHDL, Verilog.

Spectroscopic Ellipsometry, X-Ray Photoelectron Spectroscopy, Origin 8.1.

Operating Systems: Windows, Linux.

MS office, Matlab and Tcl.

ACADEMIA

University of Liverpool- MS in Microelectronic Systems, with 2:1(First class) in 2010.

Shadan College of Engineering & Technology (JNTU), (B.Tech) in ECE, with 62% in 2007.

Board of Intermediate Education, Intermediate, with 86% in 2002.

Board of Secondary Education, S.S.C. with 84% in 2000. PHYSICAL DESIGN TRAINING

Chip edge technologies Feb-2014 to June-2014

Tool Used: Cadence SOC Encounter.

Technologies worked: 90nm, 180nm.

Entire Physical design flow - Floor planning, Power planning, Placement, CTS, Routing, Timing closure, DRC-LVS. Project DTMF Leon Ethmac

Technology 90nm 90nm 180nm

No. of clocks 8 2 3

Macro count/Instance count 4/4000 12/36000 2/9000

TEACHING ASSISTANT University of Liverpool Aug-2011 to Feb-2013 Responsibilities include:

Teaching assistant for Advanced Analog Integrated Circuits (Cadence Tools) and Digital systems design Labs.

Involved in designing a basic set of assignments and examination papers.

Helping with designing a more extensive set of assignments and projects.

Assessment of Assignments and Exam papers.

Attending Technical Seminars and Staff meetings in the department and serve on committees as required.

Taught several laboratory sections and a course for non-majors.

Summarising Technical papers.

MS PROJECT (3nm, 6nm LaLuO3 Thin Films)

Title: Lanthanum based ternary oxides for the end of CMOS era.

The project deals with the fundamental properties of lanthanum based ternary oxides LaxM2-xO3 (M = Sc, Lu and Y) to fulfil the requirements of gate dielectrics, an alternative to silicon dioxide.

The main focus was on one of the ternary oxide Lanthanum Lutetium Oxide (LaLuO3). 3nm and 6nm LaLuO3 Samples were investigated.

In this the key parameters oxide thickness, leakage currents, bandgap structure and interfacial layers were studied.

To achieve this Spectroscopic Ellipsometry, X-Ray Photoelectron spectroscopy were used. Electrical characterisation was used to study the capacitance-voltage and current-voltage characteristics. RELAVANT COURSE WORK

Design of circuit schematic and layout of basic CMOS logic gates (Inverter and NAND). Technology used: Two level metal, two level poly-silicon P-Well CMOS with 1.5 um feature size. Introduction to composer schematic and Layout editor. Designed according to given specification. Study of Inverter for different drive strengths and Loads. Did DRC, LVS and Parasitic extraction. Also learn about different steps involved in custom layout flow. Tools used: Schematic composer, Virtuoso XL.

Design of circuit schematic and layout of Master-Slave JK Flip-flop and Decade counter. Technology used: Two level metal, two level poly-silicon P-Well CMOS with 1.5 um feature size. Designed a Master-slave JK Flip-flop and checked with SpectreS. Created the layout view run DRC and LVS. Similarly designed a Decade counter which counts from 0 to 9. Did DRC and LVS. ACTIVITIES and INTERESTS

Participated in an industrial tour to Bharath Electricals Limited (BEL), Bangalore, as part of my under graduate study.

Played Cricket for a local club in Edge hill, Liverpool. Also like Playing Badminton, Chess and watching Football, Tennis.

Enjoy travelling, went holiday trips to Blackpool, Northumberland, Alton Towers, North Wales and Sivasamudra, Nandi hills in Bangalore with my friends. References: Available on request.



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