Minh Vu

**** ********* ***

San Jose, California 95121

act7zc@r.postjobfree.com

Cell 408-***-****

Home Phone 408-***-****

Career Objective:

Seeking for Hardware Engineering/Tech for NPI, R&D, Lab technical support or RMA Failure Analysis is related to technical skills and experienced in Lan, Wan networking position, which will offer an opportunity for advancement and development of my career in the Networks Electronics fields.

Experience

Hunter Technology Corp

1940 Milmont Dr Jun/05/2013 to 11/31/2015

Milpitas, Ca 95035

Supervisor: Frank Prysad

Cell: 408-***-****

Position:

Sr, Network Hardware LabTest Engineering-Tech :

Responsible all kaleiderscape & Nervo System products and generated yield criterion standard for the quality group, support Box Build productions and field return failure analysis RMA for all customers, also responsible for new Customers Windows software configuration.

-Perform Failure Analysis on devices to address customers concerns and help solve internal or yield issue. Create a standardized FA/Root cause process report for each issue with findings conclusions and proposed follow up actions.

-Familiarity with operation and application of analytical tools such as common Lab equipment (scopes, data generators, curve tracers) and, bench testing. Program firmware JTAG, Data I/O prom/gal, SanDisk, Flash Card and ISP program.

- Debug down to components level & rework PCB for special tools for FPGA & BGA

I always be a team player, able to work well with others in the Lab and successfully under pressure.

Intel Corp

3600 Juliette Lane

Santa Clara, Ca 950**-**-**-**** to May-31-2013

Supervisor: Blain Thomas

Intel Office: 408-***-****

Position: Sr: Hardware Engineering/ Technician:

As a Sr, Hardware Engineering Lab Technician my responsible towards low power DC measurements of 8 cores voltage rail and voltage drops, collecting all data, power work-loads interfaces and usage of power measurement models: 2680A Fluke, 2645A Fluke, Net-DAQ, and National Instrument NI-PXLE 1062E.

My responsible for all Intel Products in the Lab is:

- Operating Linux system & Boards bring up, rework and install Software Windows upgrade

- SV system builds where 20+ interfaces are exercised

- System boot up Test with Linux and measurements the cards for all updates

- Run all Spec CPU Automation test differences CPU test speed and 8 cores collecting all differences power DC voltages Work-loads of all Intel Tablets PTU, Mobile PTU and Micro-server PTU such as:

- Idle test, Prime95 test, Cine-bench test, Lin-pack test, Spec CPU test

- Cache bandwidth, memory DDR2 test.

- IP upgrades like BIOS/FW/OS-Image - test card firmware, Program JTAG, Data I/O prom/gal, SanDisk, Flash Card and ISP program.

- Support our customer staff engineers and developers-

- Debug down to components level & rework PCB for special tools for FPGA & BGA

I always be a team player, able to work well with others in the Lab and successfully under pressure.

Jabil Inc

30 Great Oaks Blvd 8/19/2008 to 12/01/2011

San Jose, Ca 95119

Supervisor: Jose mendoza

408-***-****

Sr, Network Hardware Test Engineering-Tech :

Responsible all McAfee products and generated yield criterion standard for the quality group, support Box Build productions and field return failure analysis RMA for McAfee customers, also responsible for new Customers software configuration.

Provide for all Automation software development Linux, Unix test and debug Hardware Analog/Digital circuitry down to components level and rework with highly skill in hands soldering SMT, responsible for all Box Build products of I-Series and M-series System and pilot build Gigabit ports Ethernet switch, as well as Microprocessor Verification: debugging of RISC super scalar of deep pipe lined or multi-threaded microprocessor designed for family of : Intel, NVidia, Sun, ARM, MIPS, various linear and mixed-signal FPGA integrated circuits on McAfee products Mission, Larson, Wilson & Paloma of M-series, of Ethernet Gigabits Switch family. Which is Responsible for identifying problems on Token ring bridge, Captures of send and receive Data packets lost on system Smart bit traffic test?

- Expertise with test automation framework development.

-Familiarity with real-time handling (sample rates, buffering, PCM, drivers).

-Identifying, reproducing, and isolating issues; work with engineers on investigating and debugging failure issues in test ORT, Hass and ESS with Hot/Cold cycles test with highly-complex problems.

-Defining and updating team testing, processes, procedures, and new build stack test stations.

-Provided R&D technical support product and debug training to Production Tech, assisted and accomplished in highly troubleshooting of Analog/Digital circuitry down to component level boards with Schematic Capture tools with Mentor Dx-Designer and Cadence PCB Editor (a.k.a. Allegro).

-Perform Failure Analysis on devices to address customers concerns and help solve internal or yield issue. Create a standardized FA/Root cause process report for each issue with findings conclusions and proposed follow up actions.

-Familiarity with operation and application of analytical tools such as common Lab equipment (scopes, data generators, curve tracers) and, bench testing and Program JTAG, Data I/O prom/gal, SanDisk, Flash Card and ISP program,

- Debug down to components level & rework PCB for special tools for FPGA & BGA

Education and Training:

- AA degree of General Education De Anza College in Cupertino.

- AS degree of Electronic Technician Micro Polytech (Graduated 1992),

- Major electronics technology courses taken:

- AC/DC theory lab, Boolean algebra, solid-state devices, Digital circuit, Microprocessor base system (68000, 8088, 80186, 80256 etc) physics for electronics and basic programming.

- Certificate of Riverstone Networks Router in 2000.

- Certificate of completion through Microsoft Windows

- Certificate of completion for Unix System Advance (1998).

- Certificate of completion for Microsoft Window NT4.0 workstation (1997)

- Certificate of completion for Microsoft Word 4.0 version (1992)

- Certificate of completion for Protocol Principles Design of networking seven layers (1991)

- US Citizen.

REFERENCES FURNISHED UPON REQUEST.

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