VLsi Ip and SOC verification engineer

AQUIB QURAISHI

M.Tech in VLSI Design

C-***, Salman building, opp- Noor masjid

Sec 9A, Vashi, Navi Mumbai 400703

Maharashtra – India

E-mail: ***************@*****.***

Phone no: +91-958*******/+918*********

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible.

Currently working as a SoC and IP verification intern using system verilog and UVM in Manjeera digital system since august 2015.

EDA Tool : Cadence-virtuoso, Cadence - nc launch(for asic design and ip verification), Cadence RTL compiler, Cadence encounter for place and route, Xilinx ISE, Xilinx Vivado, Questa sim

Hardware Description Languages: : Verilog, System Verilog &UVM method(basics)

Scripting language : Perl

FPGA Based System Design

Sound knowledge on CMOS basics and Low Power CMOS VLSI Design,

Crystal clear on ASIC Flow, ASIC design of digital circuits, RTL synthesis and logic design

Expertise in front end design using VERILOG and efficient in Perl scripting

Sound knowledge and huge interest in digital circuit designs and ASIC design and verification

Basic knowledge on system verilog and UVM methodology for verification.

Promoted as a setup – lead test engineer on international Qualcomm China project

Handled the setup with great appreciation from client in China

Published a Technical Paper in international journal of science and engineering research

PROJECTS (MTech):

INTERNSHIP PROJECT: SoC and IP verification using system verilog and UVM

Tools used : Questa Sim (Mentor Graphics).

Description:

Verification of all IP blocks on SoC using system verilog and UVM methodology

Executing various test cases to verifying functionality of the IP using system verilog and UVM

Successfully developed UVM environment for protocol verification of AXI BUS, HDMI,DMA

Develop environment and execute test cases to verify functionality of proprietary IP (UMA) which can act as coprocessor for image processing

Study the coverage reports and find the bugs in the design of UMA functionality

Execute the system level verification of SoC and communication of all IP in SoC

he So

SEM1 : Area efficient FPGA based LDPC decoder using Stochastic decoding scheme

(Accepted and published in international journal of science and engineering research, vol6 march 2015)

Tools used : Xilinx for verilog coding and simulation

Description:

Aim of the project is to design of an area efficient LDPC decoder with reduced complexity and reduced size for wireless communication device.

Successfully implemented LDPC decoder used for error correction, thus providing stability to wireless devices like Wimax. .

Decoder designed here consumes less area, less complexity and can be easily implemented in practical applications.

The number of slices consumed was further reduced by effective coding scheme and the modified algorithm.

SEM 2: Project: ASIC implementation of Piecewise-Affine Functions Defined Over General Partitions.

Tools used : Xilinx and cadence nc-sim for Verilog coding and simulation.

Cadence RTL compiler : To obtain synthesis results and study different parameters Cadence SoC Encounter: To obtain place and route and generate layout.

Description:

Implementation of a programmable and configurable architecture in (ASIC) to generate Piecewise-Affine (PWA) functions

Successfully simulated the RTL for PWA function using Cadence nc sim and verified its correctness by studying its waveforms

Successfully synthesized the design and net list generation of design,studied the timing delay power reports, area using Cadence RTL compiler

Cadence SoC encounter tool was used for place and route and an optimized design layout was successfully obtained.

Project

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