Project Engineer

CURRICULUM VITAE

Yogendra kumar Sharma A-***

Gali No-1 Rama garden

D.O.B- 19 Nov 1991

Karawal Nagar Delhi-110094

Phone:0-989*******,0-989*******

******************@*****.***

Objective

I want to build my career with an organization where my skills and

knowledge can be put to effective use leading to the progress of the

company and my own enrichment in personal and professional manner.

Education

Completed PG-Diploma in Integrated VLSI & Embedded System from CDAC Noida

with aggregate 78% without any backlog.

Year Institute/University

Percentage Level

2015 CDAC Noida

77.81 PG-Diploma

2009-13 Om Sai Institute of Technology & Science

73.56% B.Tech(ECE)

2008 Govt. Boys Sr. Sec. School No.-2,Roop nagar Delhi

65.2% Class XII

2006 Govt. Boys Sr. Sec. School No.-1,Roop nagar Delhi

66.6% Class X

Technical Skills

Programming Language known : Verilog,VHDL,AVR,ARM,C,C++, Shell scripting

Software Tools : AVRSuit 3.3, KEIL ver. 4 Tool by ARM, Proteus

Design Suit ver. 7.7, Project Navigator by XILINX, Modeltech Simulator ver.

10.1b, LabVIEW, Matlab.

Professional Experience

One Year experience as SERVICE ENGINEER in ABACUS SOFTECH LTD.

Working with ABACUS SOFTECH LTD.from NOV 2013 to OCT 2014,

Extensive hands-on experience in Maintenance of Biometric Attendance

system, maintenance of customized software and registration, validation of

Mifare Desfire cards.

Extensive hands-on experience in Acceptance test for newly installed

Biometric readers

Installation of Server for Biometric Attendance System.

Communication with Card Readers.

Academic Projects

Title :IMPLEMENTATION OF SERIAL COMMUNICATION PROTOCOL (SPI) USING VERILOG

Platform : VLSI Design

Duration : 2 Months

Description : This project are used to serial communication protocol to

exchange information between different electronic embedded devices.This

project describes the development & implementation of this protocol using

VERILOG.For the implementation of this protocol, it was taken into account

different modes of operation, such as master/slave mode sending or pending

data mode.VERILOG work to implement and simulate these communication

protocol with the software version of Modelsim SE 10.1b.

Title : Audio Surveillance system using DTMF technology

Platform : Embedded System Design

Duration : 6 Months

Description : The main idea is to design a robot with control in our

hand.So,that we can make it to move in any direction & this robot will be

used for multiple purpose due to audio transmission on it & availability of

different modes of functionality & it will work for surveillance purpose as

it will detect the surrounding with the help of sensors & this robot is

controlled by DTMF i.e a mobile phone through DTMF & DTMF modes are used to

control the movement of robot.So,it is to give audio signal as a result

Vocational Training

6 weeks Industrial Training at DRDO, Delhi

June-July 2012

Done project named as "FILTERING AND PEAK DETECTION OF LIDAR SIGNAL" using

LabVIEW software.

PCB Designing in College Campus

June-2011

Done training in designing of PCB (printed circuit board).

Theory and practical classes were attended in college campus.

Extra Curricular Activities

Have attended seminar in Cyber Crime.

Have attended seminar in Robotics.

Personal Information

Father's name : SH. KRISHAN GOPAL SHARMA

Marital Status : Single.

Nationality : Indian.

Languages Known : English, Hindi.

Hobbies

My hobbies include watching cricket, listening music, surfing, and guiding

students in academics

I hereby declare that the above mentioned information is correct and upto

my knowledge.

Dated:

(Yogendra Kumar Sharma)

Place: Delhi

Contact this candidate