Design Project

MORAMPUDI.HARI BABU Mobile: 950-***-****

Email id: *********.********@*****.*** .

Career Objective :

Seeking a position in a well-defined process oriented organization where my technical

and communication abilities are fully utilized and recognized also to improve my

professional skills there by contributing to the growth of the organization.

Professional Summary:

Having around 2+ years of experience on Digital System Design & Programming

of FPGA & ASIC using Verilog HDL & VHDL.

Experience on writing VERILOG behavioural models & Functional Verification.

Experience in Digital circuits design on FPGA Spartan 3E board.

Experience in ASIC Design.

Experience in RTL coding, Test Bench creation, Simulation, Synthesis & Place

and Route.

Experience in XILINX ISE 9.2i & 10.1.

Experience in developing design specs, HDL based RTL.

Strong in Digital System Design Fundamentals.

Educational Qualification:

B.Tech (EEE) from Jawaharlal Nehru Technological University, Hyderabad.

Experience Summary:

Working as Digital Design Engineer in VAJRA POWER CONVERSIONS

From September 2013 to Till date.

Professional Courses:

Program Language: C language.

Hard Ware Description Languages : Verilog HDL & VHDL.

Tools : XILINX ISE 9.2i & 10.1 ISE SIMULATOR & MAT LAB SIMULINK .

P UBLICATIONS & CONFERENCES:

“RTL Design and VLSI Implementation of an efficient Convolutional Encoder

and Adaptive Viterbi Decoder using Verilog HDL” published in ICIECE-2014

Conference held at GNIT-HYDERABAD.

Project Summary :

Project Title #1:

RTL Design and VLSI Implementation of an efficient Convolutional Encoder

and Adaptive Viterbi Decoder using Verilog HDL.

Description: This project focuses on the realization of an efficient logic design of a crypto

system. The type of crypto system considered in this project is convolutional encoder and

adaptive Viterbi decoder (AVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2

using field programmable gate array (FPGA) technology. Here, the features of Convolutional

encoder and decoder architecture are introduced and the way it can be implementable as an

ASIC.

Role: Writing Verilog HDL code and FPGA Design.

Project Title #2:

Design, Modeling and Implementation of an Intelligent Automatic Chocolate

Vending Machine (AVM) using Verilog HDL.

Description:

A simple digital circuit is to be designed for the coin acceptor of an electronic chocolate

vending machine.Assume that the chocolate cost 10 rupees.

Role: Writing Verilog HDL code and FPGA Design.

Project Title #3:

TRAFFIC LIGHT SIGNALS.

Description:

Generally we know about traffic signals but here we operate the traffic signals by using

Verilog HDL code. When the clock and reset place a crucial role for the signaling. By enable

of these parameters only the lights i.e. red, green, yellow can be changes it’s state.

Role: Writing Verilog HDL code and FPGA Design.

M ajor Achievements :

Organizer for the college discipline committee.

Conducted several events in college such as association’s activities NETWORK’12.

Strengths :

Team spirit & Team Work.

Positive & Quick Learning.

Creative &Hard work.

Patience & Obedient.

Declaration:

I hereby declare that the above information furnished is true to the best of my knowledge and belief.

Place: Hyderabad

Date: (MORAMPUDI.HARI BABU).

Contact this candidate