digital design

RADHIKARAMYA PAKALAPATI

M.Tech (VLSI Design) H.No:9, Shreerangam

Near WASA Layout, Doddanekundi

Bangalore - 560037

E-mail: ************@*****.***

Contact No: +91-974*******

Summary:

3.5 Years of Research and Teaching experience in the field of VLSI Design and Digital IC Design applications.

Mentored graduate students for the course projects in the field of VLSI Design.

Experience in digital design applications using Xilinx ISE design suite.

Experience in CMOS VLSI design, ASIC design and in Physical Design Flow using CADENCE.

Expertise with FPGA Spartan kits and Chip Scope Pro- Analyzer. Career Objective:

To work in an Organization that can give me continuous growth and helps me to explore my skills and knowledge towards achieving organizational goals and objectives. Academic Profile:

Degree/Certificate Year Institute/School, location CGPA/% M.Tech.

(VLSI Design)

2011 Hindustan University, Chennai 8.48/10

B.Tech.

(ECE)

2009 Sasi Institute of Technology & Engineering,

Tadepalligudem (Affi. to JNTU Kakinada)

71.2%

Intermediate

(Maths-Physics-Chemistry)

2005 Sri Sai Chaitanya Junior College, Eluru, 87%

Class X

(S.S.C)

2003 Sree Sree Educational society, Eluru. 78.9%

Software Proficiency:

Operating Systems: Windows, Linux.

Languages: C.

VLSI Programming Languages: VHDL, Verilog HDL.

VLSI Programming Tools: Xilinx 13.1

Layout Tools: CADENCE (Virtuoso, Assura, Spectra). Work Experience (Academic and Research):

Institute: Vignan Univeristy, Guntur, Andhra Pradesh Designation: Assistant Professor - School of Electronics (From July 2011 – November 2014) Courses Taught:

VLSI Design Digital IC Design

VLSI Digital Signal Processing

Digital Electronics

Digital Design through Verilog Switching Theory and Logic Design Projects Guided:

Design of Tunnel FET Based Ultra-Low Power and High Efficiency Power Management Circuits for Energy Harvesting Applications.

FPGA Implementation of Low Power Digital FIR Filter based on low power multiplier, adders. Publications:

1. Presented a paper on “Optimization of Reversible BCD Adder in Terms of Number of Lines” in International Conference on Information Communication & Embedded Systems at S&A Engineering College, Chennai in February, 2011.

2. Published a paper on “Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines” in International Journal of Application or Innovation in Engineering & Management (ISSN 2319 – 4847), Volume 2, Issue 9, September 2013. 3. Presented a paper on “Implementation of Energy Efficient and Low Complex Filters with Re- configurability Usage” in International conference “NSSP-2013” at ANU, Guntur. 4. A paper on “Designing Ultra-Low Power and High Efficiency Power Management Circuits for Energy Harvesting Applications with Emerging Nano Scale Devices” is under review in IEEE. Workshops Attended:

Two weeks workshop on “Analog Electronics” conducted by IIT Kharagpur.

“VLSI Design using cadence tool” at Vignan University, Guntur.

“FPGA based Digital and Embedded System Design” using Xilinx at Vignan University, Guntur.

“IUCEE Advanced Digital Signal Processing” at Vignan University, Guntur. Academic Projects:

M.Tech Thesis at Hindustan University, Chennai

Title: “Optimization of reversible BCD Adder in Terms of number of lines” This work involves development of minimal energy dissipation by using reversible logic and this can be achieved by reducing the number of garbage outputs with appropriate constant input lines by using optimization algorithm, under the supervision of Prof. Raj Mohan. The developed modules have been validated with the literature and implemented using FPGA. Extra-Curricular Activities:

Coordinator for conducting seminars, group discussion for UG and PG students.

Member of the organizing committee for technical exhibitions and departmental fest. Personal Details:

Date of Birth : 11

th

June 1988

Sex : Female

Marital Status : Married

Languages Known : Telugu, English and Hindi

Declaration:

I hereby declare that the information furnished above is true to the best of my knowledge. Place: Bangalore

Date: 29/05/2015 P. RADHIKARAMYA

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