Software engineer

Vineesh Kumar K.K

Summary:

Design and development of power delivery software. Power and performance analysis/optimization of various workloads on Intel SoC. Software tools development for SoC architecture analysis.

Publications:

Shipping an IA Smartphone

oIntel Fellows’ Power Conference, Feb 2012.

<Architecture tool> for Power analysis and modeling.

oIntel low power conference, 2010.

Optimization and analysis of browsing UC power on wireless environment.

oIntel wireless conference, 2011

Intelligent charging model for improving the battery longevity

oDTTC, 2015.

Awards:

oAccomplished 4 DIVISIONAL RECOGNITION AWARDs. And many spontaneous recognition awards.

Employment Record

July 2005 – till date

Organization: Intel Corporation, Bangalore.

Position: Software Engineer.

Power delivery and Energy Management:

Roles:

oModule design and development of Linux drivers for PMICs, battery charger, fuel-gauge and charger dock solutions.

oInstrumental in enabling the power delivery software on Dell Iconic.

oSuccessfully delivered the power delivery software for battery, charger and PMIC on Clovertrail, Merrifield and Moorefield platforms.

oDesign and development of intelligent charging model for improving the battery longevity.

oDesign and implementation of context aware charging algorithm with the accuracy of 80%.

oDesign and implementation of A4WP/REZENCE wireless charging.

oA4WP/rezence protocol implementation in kernel driver.

oDriver for wireless power receiver.

oUse case definition for wireless charging.

oContribute to software architecture documents. Schematic review.

oGood understanding of power supply class, I2C and SPI.

oActive participation in platform power on.

oRepresented power delivery software team for power-on of the latest Intel platforms.

oPropose PoCs and prototype implementation.

oImplement the software on evaluation kit.

oExperiment new charging technique.

oLead the power delivery feature integration effort on the platforms.

oLead the use case integration of power delivery software on the platform at different stages of the projects.

Position: Systems engineer,

POWER AND PERFORMANCE ANALYSIS AND OPTIMIZATION.

Platforms: Menlow, Moorestown, Medfield, Clovertrail+.

Languages: C, C++ and X86 assembly.

Roles:

oSoftware tools development for SoC architecture analysis. System power and performance analysis on Intel SoC.

oDesigned and developed tool for getting CPU C/P States, memory bandwidth and SoC sub-system residencies.

oDesigned and developed tools for getting modem states DCH/FACH/PCH.

oInstrumental in shipping the first Intel IA-SoC based phone product with competitive power/performance figures.

oActively involved in reducing the platform standby power by 10x for Medfield.

oPlatform rail level power measurement and analysis.

oSubmitted a paper at internal and external conferences.

oEmbedded Linux conference presentation link for details.

oPerformance analysis of various use cases, browsing, 2D graphics and HTML5, Video streaming, CPU benchmarks.

oAnalysis of L1, L2 cache size impact on software performance.

oPerformance analysis using Vtune, Ftrace and PVR-tune.

oPerformance analysis on FISHTANK HTML5 benchmark.

oPnP analysis of video streaming and video playback.

oPower and performance optimization of system standby power, HTML5, Flash Video streaming and browsing.

oVideo/FLASH FPS measurement tools.

oApplication response time measurement tool

oOptimization of flash video streaming power.

oBrowsing power optimization on chrome browser.

oThe power and performance projections. Workload definition and development.

oDefined and created browsing workload, works across the OSes.

oHTML5 workload development.

oDeveloped different versions of the Fishtank benchmark for GFX 2d performance analysis and optimization.

oPower projection using subsystem residencies of various use cases.

oProfile-guided optimization of standard CPU benchmarks like EEMBC, Core mark, HINT and SPEC.

oFind the right combination of compiler flags for getting the best score for CPU benchmark.

oProfile guided optimization using intel compiler

oConduct architecture experiment for evaluating the architecture features. Review with senior architect/Fellow.

oCompetitive analysis on power and performance of various platforms.

Technical Skills Set

Programming Languages

C, C++, Java for android.

VB, Hi-tech C

X86 assembly.

Operating System

Linux and Android.

Architecture

IA.

Qualification:

M-TECH IN SOFTWARE SYSTEM (BITS WILP) Pursuing.

MCA in computer science from Sikkim Manipal University, GPA: 68% (Distant Education).

Diploma in Computer engineering from NTTF., GPA: 78%.

Personal Details:

Surname : karuvankandy.

Nationality : Indian.

DOB : 16/04/1983

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