System Verilog, Uvm,Verilog,Perl

HAREESH BABU POTHINENI

+91-984*******,Email: harishbabu.pothineni@gmai

Carrier Objective

Seeking a good career where my technical knowledge and analytical skills will be utilized for the growth of the organization in addition to providing me a good learning opportunity.

Technical Skills

Software Language

Verilog, System Verilog

Methodology

Universal Verification Methodology(UVM)

Operating System

Windows-XP, Linux

Tools Used

Questasim(Mentor Graphics),Modelsim

Subjects of Interest

ASIC design flow & verification, ETHERNET protocol

VLSI Training:

Course: Advanced ASIC Verification.

Institute : ExpertHDL Training and Consultancy Services, Bangalore.

Duration: June 2014 to December 2014.

Educational Carrier

Degree

Year

School/College

University

Percentage

B.E.(Electronics

&Comm. Engg.)

2014

ST.ANN’S ENGINEERING COLLEGE

JNTU

72

Intermediate

2008

SRICHAITHNYA BHARATHI JUNIOR COLLEGE

BOI

86

S.S.C.

2006

VIKAS HIGH SCHOOL

SSC

86

Projects during Training:

Developed the design for UART in verilog and developed with the help of system verilog.

Developed the Verification environment for AMBA-APB memory interface in UVM.

Developed the verification environment for 10gig pcs ip and verified it.

Protocol knowledge on 1gig Mac(media access control layer)

1)Project Name

Design and verification of UART Controller

Description

UART is a popular serial asynchronous communication to connect the processor and a peripheral. It essentially consists of transmitter and receiver and interrupt controller. Transmitter generates the UART frame and sends the serial data with baud rate of maximum 3Mbps. Receiver also have 256 byte deep FIFO of each 8 bit wide and generates the interrupts to the processor as and when the data is ready in FIFO and also when it receives errors.

Contribution

Understood the standard specification.

Involved in building the verification environment.

Prepared test plan as per requirement.

Wrote test cases .

Language/Methodology

System Verilog.

2)Project Name

AMBA APB

Description

The APB is part of the AMBA protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface. The APB has un pipelined protocol.

Contribution

I have studied the SPEC defined by AMBA.

Involved in building the verification environment.

Prepared test plan as per requirement.

Wrote test cases.

Language/Methodology

UVM

3)Project Name

10gpcs ip verification

Description

PCS IP has XGMII interface to transmit and receive data from MAC Layer.

It also has XSBI interface to transmit and receive data to and from Serdes Layer respectively.

It also has MDIO interface to configure its registers.

It also have 64b/66b encoding technique in order to achieve synchronization with the remote device.

contribution

Understood the standard specification.

Involved in building the verification environment.

Prepared test plan as per requirement.

Wrote test cases .

language/Methodology

uvm methdology

Protocol knowledge on 1gig mac:

Description:

Ethernet is layered protocol which spread across MAC and Physical Layer of seven layer OSI model. It supports multiple data rates start from 10Mbps to 100Gbps.

MAC IP has Application Layer interface which Receives and Transmits raw data to Upper Layer.

Also has GMII interface which transmits and receives Ethernet Frames To/From PCS.

It has AHB configuration interface, to configure the MAC for required functionality and to Read the status from the Status registers.

B.Tech Project:

Project: DUAL PORT RAM IP VERIFICATION IN SYSTEM VERILOG.

Extra activities:

Participated in verification forum conducted by mentor graphics

Participated in verification forum conducted by altium,arm.

Personal Information:

Date of Birth : 16th January 1993.

Sex : Male.

Nationality : Indian

Addresss :Amani PG,13th main,14th cross, sector-4,Bangalore.

Linguistic Abilities: English and Telugu .

Declaration:I hereby declare that the information furnished above is true to the best of my knowledge.

Hareesh pothineni

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