Design and Verification endineer

PALLAVI PARMAR Phone: +91-782******* *th main,*th cross BEML layout Email: ***************@*****.***

Kundalhalli Bangalore - 560066

CAREER OBJECTIVE

Aspire to take technical challenges in the globally competitive environment in field of VLSI design and verification that yields twin benefits of the job satisfaction and steady pace professional growth.

WORKING EXPERIENCE

Worked as a Design and verification engineer at Incise InfoTech Pvt. Ltd. Noida (U.P.) Since Sep 2012-sep 2015.

SKILL SET

HDL :Verilog,VHDL

HVL : System Verilog,

Verification methodology : UVM (Basics)

Tools : Mentor Graphics Design Architect [TSMC 35], Eldo, IC Station, Calibre, ModelSim, Questasim.

: Silvaco for MOSFET modelling and simulation.

: Xilinx ISE 12.1 design suit.

INDUSTRIAL PROJECTS DONE

Project 1: AMBA AHB Slave (Design and Verification).

Designed and Verified the AMBA AHB Slave protocol for a General Purpose Micro-Controller based platform.

Design has been implemented for high bandwidth operation. Completely generic IP (can be ported to any system easily).

Roles and Responsibilities:

Created a test environment for the verification of the protocol.

Created driver, scoreboard, monitor, models for the verification of the protocol.

Created test-cases for the verification.

Written cover properties to determine the Functional Coverage.

Project 2: AXI (Advanced eXtensible Interface Bus) Slave (Design and Verification).

Thorough understanding of the design specification and timing analysis. we designed the AXI slave interface using Verilog and verification using System Verilog. AXI is a bus protocol introduced in Advanced Microcontroller Bus Architecture published by ARM Ltd Company.

Roles and Responsibilities:

I worked with AMBA AXI protocol Verification as a team member .

My responsibilities are comes under developing Response Checker.

Project 3 : Development of APB (Advanced Peripheral Bus) protocol.

The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power Consumption and reduced interface complexity.

Roles and Responsibilities:

Study of APB protocol, and documentation done.

Developed RTL in Verilog.

ACADEMIC CREDENTIALS

Qualification

Year of passing

Institution

University/Board

Percentage/CGPA

M. Tech.

VLSI Design

2012

Amity University, Noida

(U.P.)

Amity University, Noida

(U.P.)

7.14[CGPA]

M.Sc.

[Electronics]

2007

Jiwaji University, Gwalior

(M.P.)

Jiwaji University Gwalior

(M.P.)

65%

B.Sc.

[Electronics]

2005

Govt. K.R.G. college, Gwalior (M.P.)

Jiwaji University Gwalior (M.P.)

61%

Higher Secondary [12th]

2002

Govt. H.S. School, Gohad

(M.P.)

M.P. Board Bhopal

77%

High school

[10th]

2000

Govt. H.S. School, Gohad (M.P.)

M.P. Board Bhopal

76%

ACADEMIC PROJECTS AND CONFERENCE

M. Tech(4th sem.)

Overview- Thesis on “Analysis and design of Adiabatic Sense Amplifier for SRAM” from CDAC Noida

Team size - 2

Duration - Feb-June 2012

Attended two days National Conference on ‘VLSI, MEMS & NEMS’ (September 23-24, 2010) at Amity University Noida.

ACADEMIC ACHIEVEMENT

Selected in CMC Limited (TATA Enterprises) on basis of M.Sc.

DECLARATION

The information given above is true to the best of my knowledge and belief.

Place: Bangalore Pallavi Parmar

Date:

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