Engineer Design

SUMMARY

Over ** years of experience in ASIC front end and FPGA design/verification, from design specification to production. Solid background in DSP and image processing. Specialty in VHDL, Verilog, Matlab, C, Altera and Xilinx FPGA design, and Modelsim simulation and Synopsys Design Compiler, etc. Experience in performing lab debug using oscilloscope and logic analyzer. Pre and Post-sales technical support. Medical Device GMP and FDA Regulations experience.

PROFESSIONAL EXPERIENCE

STMicroelectronics – Piscataway, NJ

Senior Hardware Engineer 2011 – Present

Front-end ASIC design and verification of PLC (Power Line Communication) wide band and narrow band ASICs

•Participated in post-silicon bring-up, test and debug of StreamPlug ASIC.

•Performed feasibility study plus Matlab and VHDL modeling for Turbo Decoding.

•Developed and simulated with Modelsim VHDL Channel Deinterleaver functional block.

•Implemented RTL Functional Verification with eVC Cadence for narrow band ASIC.

•2 patents were filed in 2013.

Abbott Point of Care – Princeton, NJ

Senior Manufacturing Engineer 2008 – 2011

Pre and post-sales support in the production of i-STAT portable handheld blood analyzer and associated peripherals (simulator, downloader/recharger, and printer)

•Performed manufacturing/testing equipment troubleshooting

•Proposed and implemented process improvements for manufacturing floor efficiency and to generate higher product yields.

•Investigated customer complaints, resolved product quality issues and drove process improvements and regulatory compliance.

AMD – Yardley, PA

Senior ASIC Engineer 2004 – 2008

Design and verification of SoC ASIC used in video/computer graphic application and LCD panel.

•Conducted ASIC chip level memory BIST insertion and verification.

•Designed several function blocks on a number of SoCs by collaborating with system engineers to specify blocked functionality and designing and verifying blocks through RTL coding, logic synthesis, functional verification, formal verification, and static timing analysis.

•2 patents were granted on 11/16/2010 and 08/21/2012.

Multilink Tech. Corp. – Somerset, NJ

Senior Application Engineer 2001-2004

Design and verification of FPGAs for Forward Error Correction ASICs evaluation board

•Managed all phases of FPGA design by coordinating with multiple functional groups to develop design specifications that satisfied the requirements of all stakeholders and implementing FPGA in VHDL, creating test plan, developing test-bench, and configuring and debugging FPGA on evaluation board.

•Developed application notes and reference designs based on the request of internal and external customers from China.

Viagate Tech Inc. – Bridgewater, NJ

Hardware Design Engineer 1999-2001

Hardware design of VDSL CPE board

•Implemented Verilog coding, synthesis and simulation of CPLD/FPGAs residing on VDSL CPE board.

•Developed firmware for CPE product including flash memory driver, system configuration with Virata’s Helium communications processor, Broadcom’s DSL transceiver, NEC ATM25 transceiver, and IDT ATM25 transceiver.

General Data Comm. Inc. – Middlebury, CT

Hardware Design Engineer 1998-1999

CPLD/FPGA design T1/E1 and OC-3/OC-12 Line Interface Module (LIM) of ATM switch

•Designed the digital circuit interfaced to microprocessor on LIM cards including FLASH memory, DRAM, reset, debug, CPLD/FPGAs, etc.

•Developed and implemented sub-system test plan for LIM cards.

ADC Telecommunications – Minneapolis, MN

Hardware Design Engineer 1996-1998

•Performed VHDL functional verification for the front-end of HFC (Hybrid Fiber Coax) system, including RTL coding, synthesis, mapping, and placing/routing targeted in FPGAs.

University of Minnesota – Minneapolis, MN

Research Assistant 1994-1996

•Developed, implemented and simulated algorithms in DSP, mainly in image compression.

•Performed VHDL coding, synthesis, timing analysis, DFT, placing/routing and layout using Mentor Graphics tool set.

Shanghai Jiao Tong University – China

Assistant Professor 1990-1994

•Participated research projects in the areas of image processing and computer graphics.

•Supervised undergraduate students.

PATENT FILED and APPROVED

[1]. “Video Luminance/Chrominance Separation”. Don Wu, Robert Prozorov, Jenny (Huijuan) Liu, Christopher Jurado, Daniel Zhu and Binning Chen. 2005. Granted Patent Number 8248536 on 08/21/2012.

[2]. “SCART Input Video Signal Processing”. Don Wu and Jenny (Huijuan) Liu. 2006.

Granted Patent Number 7834935 on 11/16/2010.

EDUCATION

MSEE, University of Minnesota, Minneapolis, MN, 1996, GPA=4.0

MSEE, Shanghai Jiao Tong University, Shanghai, China, 1990, GPA=3.8

BSEE, University of Science & Technology of China, Hefei, China, 1988, GPA=3.9

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