ASIC Design Verification

M.Santhoshkumar, Phone: +91-888*******

S/o T.Mathavan, Mail id: *.*****************@*****.***

***, ******** ******, *** *****,

Bhanu nursing home road, 5th main,

Bommanahalli,

Bangalore – 560068.

.

CAREER OBJECTIVE

To be associated with a semiconductor industry that provides me boundless growth opportunities and exposure to cutting-edge technologies and learning possibilities.

PROFESSIONAL EXPERIENCE:

Working as an ASIC Design and Verification Trainee(Febraury2015 to Till Date) at CVC Pvt. Ltd, Bangalore.

TECHNICAL SKILLS

Hardware Description Language : Verilog.

Hardware Verification Language : System Verilog.

Programming Language : Perl,C.

Platforms : UNIX, Windows.

Tools Used : Modelsim,Quartus,Rivera-pro,Verdi,Onespin,Guna.

CERTIFICATION:

Certified on ASIC Design Verification from CVC Pvt Ltd.

PROJECT DONE:

CVC Pvt. Ltd:

Project1 : Designed and Verified APB Slave in Verilog.

Tools used: Modelsim and Quartus.

Scope : 1.Designed APB with no Wait states in both Write and Read Transfers of

Memory Controller of 64 bits using FSM.

2. Verified the Designed APB with Memory Controller that the Read and

Write Operation are performed in every address of the memory with the

FSM States by Using Modelsim.

3. Logic of the APB is converted into the RTL Net list using Quartus.

Project2 : Design and Verified APB Slave in System Verilog.

Tools used: Rivera-Pro and Quartus.

Scope : 1.Designed APB with no Wait states in both Write and Read Transfers of

Memory Controller of 64 bits using FSM.

2. Verified the Designed APB with Memory Controller that the Read and

Write Operation are performed in every address of the memory with the

FSM States by Using Rivera-Pro.

3. Logic of the APB is converted into the RTL Net list using Quartus.

Project3 : Debugging Simulation-Synthesis mismatch.

Tools used: Verdi3.

Scope : Simulation-Synthesis mismatch is debugged using Verdi3 by generating

FSDB files for SDRAM Controller using Questasim.

Project4 : Cell Characterization.

Tools used: Guna.

Scope : 1.Characterizing the Cells before Placement & Routing.

2. Guna tool is used to automate the characterization.

3. Guna tool will automatically generate Verilog module.

Project5 : Formal Verification.

Tools used: Onespin.

Scope : 1.Equivalence Checking.

2. Formal Verification.

3. Assertion Based Verification.

ACADEMIC PROJECT:

Project Title: GSM Based Embedded system on Irrigation.

Platform : PIC Microcontroller.

Role : Save electricity and water.

EDUCATIONAL QUALIFICATIONS

S.No.

Name of the Examination

University/Board

Year of passing

Percentage

1

B.E(EEE)

Vickram College Of Engineering, Madurai.

2014

64.98%

2

DIPLOMA(EEE)

GMS MAVMM Polytechnic College

2011

73.08%

3

HSC

Balamandiram Hr.sec.school

2009

67%

4

S.S.L.C

Psyche Matriculation School

2007

81%

SKILL SET

1. Good Communication Skills in both Verbal and Oral.

2. Eager to learn new technologies to build up my knowledge.

EXTRA CURRICULAR ACITIVITIES

1. Participated in inter School QUIZ Competition during school days.

2. Participated in various concurrent programs conducted by NSS and finished satisfactorily.

CO -CURRICULAR ACTIVITIES

1. Attended In-plant training at GENN CONTROLS OF INDIA PVT.LIMITED,

Coimbatore.

2. Attended In-plant training at BHUVANESWARI ELECTRICALS.

3. Active participant in CEG’s Technical Symposium “KURUKSHETRA”.

PERSONAL PROFILE

Date of Birth : 11th febraury 1992

Father’s Name : Mathavan . T

Gender : Male

Martial Status : Single

Nationality : Indian

Languages : English,Tamil.

Permanent Address : 89,Muniyandi kovil street,Jawaharpuram,

K.Pudur, Madurai-625007

I hereby declare that the above information is true to the best of my knowledge and belief.

PLACE: Bangalore (SANTHOSH M)

Contact this candidate