VLSI Design Engineer

Maneesh PK

*********@*******.*** +91-949******* +91-952*******

1Summary

Seeking a responsible and meaningful position as a VLSI Design engineer in a leading organization that can utilize and enhance my skills.

2Education

2013-2015

M-Tech in VLSI Design, Amrita School of Engineering

Score : 8.39/10

2008-2012

B-Tech in Applied Electronics & Instrumentation, Calicut University

Score : 67/100

2008

+2, Kerala State Board

Score: 92.8/100

2006

SSLC, Kerala State Board

Score: 92.1/100

3Core Competency

Strong skills in digital design

Good knowledge in RTL to GDS II ASIC flow

Hands-on experience with Synopsys & Cadence tools

Good idea about IC verification and testing

Sound knowledge in Computer Organization & Architecture

Superior communication skills

4Technical Skills

Language

:

C

Design Language

:

Verilog HDL

Scripting

:

Tcl

EDA Tools

:

Synopsys VCS, DC, PrimeTime, ICC

Cadence RTL Compiler, ModelSim, MATLAB

Embedded Expertise

:

FPGA, Microcontroller Programming

5Scholarships

B-Tech

:

Central sector scholarship

M-Tech

:

Gate scholarship

6Interests

Technology, Digital VLSI Design

Gaming, Travelling

7Projects Undertaken

Oct

2015

Advanced Synthesis using Cadence RTL Compiler

RISC processor is designed using Verilog HDL and synthesized with advanced set of constraints (Cadence RTL Compiler)

M-Tech

Main Project

Golden Chip Free Hardware Trojan Detection and Diagnosis

Self-consistency and self-referencing based techniques for Hardware Trojan detection and diagnosis without using golden chip. Architecture level design modifications to ensure IC security and trust

M-Tech

Term Project

Pipelined and un-pipelined processor design

Pipelined and un-pipelined RISC processors are designed using Verilog HDL and are compared (Synopsys VCS, DC)

M-Tech

Term Project

Power Optimization Using Multi Vth

Power optimization is achieved by using multi Vth library in Synopsys DC and Cadence RC

M-Tech

Term Project

Coverage Analysis of Mealy/Moore Machine

Mealy and Moore machines are designed for simple sequence detection and verified for 100% Condition, Line and FSM Coverage using Synopsys VCS

M-Tech

Term Project

Familiarization of ASIC Flow

Familiarized the RTL to GDS II design flow. A simple counter is designed in Verilog HDL. Its netlist is created, Layout is generated, Pre and post-layout timing analysis are carried out using Synopsys bundle

B-Tech

Main Project

Zero force touch frame

Turns every display or projected surface into a touch screen. A low cost touch solution with wide applications and future scope

B-Tech

Mini Project

Water level indicator and controller

An intelligent water level indicator and controller, with natural LCD display and keypad. Proficiency for limit setting and to avoid dry running

8Publication

Paper entitled "Power Based Self-Referencing scheme for Hardware Trojan Detection and Diagnosis", Presented in International Conference on Soft Computing in Applied Sciences & Engineering 2015

9Seminars

M-Tech

Double Patterning Lithography

Lithographic technique which enables fabrication of sub-30nm nodes with current optical systems. A strong candidate for 22nm/16nm technology nodes

B-Tech

Sixth sense technology

A wearable gestural interface from MIT Media Lab. Merges physical world with digital world by providing seamless real-time internet connectivity

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