Project Design

Priya Singh

Address for Correspondence:

A ** first floor

Sector 71

Noida 201301

Phone : +919*********, 971-***-****

Email : ****************@*****.***

CAREER OBJECTIVE

Sincere dedication while being exposed towards the academic working environment.,seeking professional growth while being resourceful, innovative and most important, flexible.

ACADEMIC BACKGROUND

Year(s)

Qualification – Degree

Board/University

Percentage / CGPA

2013 - 2015

M.Tech – VLSI Design

Banasthali vidyapith, Jaipur

76.70%

2008 - 2012

B. Tech

Electronics & communication

Rajiv Gandhi Technical University

76.40 %

2007 - 2008

XII

C.B.S.E.

70.00 %

2005 - 2006

X

C.B.S.E.

85.00 %

Qualified GATE 2013 with 90.4 percentile .

WORK EXPERIENCE

Company: Sine international institute of technology, Jaipur Duration: June 2015 to present

Designation: Assistant Professor

Description:

To tackle semester subjects and labs of EDC, VHDL,VLSI

To manage college Co-Curricular activities

Company: Bhabha Atomic Research Centre, Mumbai. Duration: July 2014-April 2015

Designation: Project Trainee

Description:

To perform Frontend and Backend Design of ASIC which includes schematic entry

Circuit designing,

Layout designing with DRC,LVS,DFM

Verification and testing

PUBLICATIONS

Title : Design of a Hybrid CMOS On Chip High Voltage Generator

Journal name : IJSRES March 2015 edition

Title : The concept paper on “On Chip High Voltage generator using Polysilicon Diodes”

Journal name : IJES 2015- January edition.

Indexed in AMERICAN NATIONAL ENGINEERING DATABASE

Title : VHDL implementation of DSDV Ad-Hoc Routing Protocol

Journal name : IOSR -JMCA–CSIR journals, 2014

Indexed in EUROPEAN engineering database

Title : A concept Paper on Comparative study of FPGA implemented Adhoc Routing Algorithms

Conference: ICMI 2014, Dehradun

TRAININGS & PROJECTS UNDERTAKEN

One year Internship Program (M.Tech 2nd year) Duration: July 2014-April 2015

Company: “ BARC, Mumbai,

Project Title: Design of 4 Channel Pulse Processing ASIC

Description: The aim was to Design the Channel for detecting high energy physics particle and converting it to voltage signal for its further study.

Design of on chip high voltage generator.

M.Tech (1st year) Duration: July 2013-July 2014

Company: “In house project,

Project Title: “VHDL implementation of DSDV Adhoc Routing Protocol.”

Description: Had coded for the control unit of DSDV routing protocol to minimize the operating time. which is much reduced than its MATLAB counterpart.

Summer Training Program (B.E 4th year)

Company : MindsteinTech, Banglore

Project Title: “VLSI Design”

Description:

ASIC Design using High Level Language “VHDL”

B.E (major): Wireless IR detector in the high range.

B.E(minor): Bidirectional Visitors counter.

CO-CURRICULAR ACTIVITIES

Had actively participated in IMPACT 2014 Conference in VIT Jaipur.

Had done Robotics workshop at graduate level.

Attended the HCL training Programs for Languages and Databases at graduate level.

Had done the Cadence workshop in ASIC designing at post graduate level.

Actively participated in MANIT Bhopal techfest and RoboWar .

Actively participated in Mayuk 2014 .

COMPUTER SKILLS

Programming languages : C,C++, JAVA, VHDL,Verilog

Operating systems : LINUX, Windows 98/xp/Vista

Software : MS office suit, Cadence tool, MODEL SIM, Leonardo Spectrum

AREA OF INTEREST

Software (VHDL and Verilog), madel sim simulator, Leonardo spectrum, xillinx, cadence tool

IC Designing

ASIC Designing

I here by declare that the details above are correct and true to the best of my knowledge.

Priya Singh

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