Design Engineering,vlsi engineer,digital design

SHAHSIDHAR.Y

Room no: ***

Tirumala p.g

Arakere main road mobile: 096********

Bangalur-560076 Email:*******************@*****.***

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow.

Extensive experience in writing RTL models in Verilog HDL.

Experience in using industry standard EDA tools for the front-end design and verification.

VLSI Domain Skills

HDL : Verilg

Protocols : AXI, AHB, UART, I2C, SPI

EDA Tool : Questasim and ISE

Domain : ASIC/FPGA front-end Design and Verification

Knowledge : RTL Coding, FSM based design, Simulation,

Functional Coverage, Synthesis, Static Timing Analysis

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore.

June 2015.

Bachelor of Engineering: Krishna Chaitanya Institute of Technology and Sciences, Markapur

JNTUK, Andhra Pradesh, India. Discipline: Electronics & Communication Engineering Percentage: 79.69 %( First Class) Year: May 2015

Intermediate: Narayana Junior College, Kadapa. Discipline: M.P.C. Percentage: 95.4 %( First Class)

Year: March 2011.

Research Competence

Presented paper titled IRIDIUM SATELLITE DATA COMMUNICATION NETWORK and obtained presentation award in National level technical fest BECTAGON 2K14 at BAPATLA engineering college (autonomous under ANU).

Presented paper titled SHIP AND AIRCRAFT NAVIGATION BY SATELLITE SYTEM and obtained presentation award in National level technical fest JIGNASA 2K14 at G.PULLAREDDY engineering college (autonomous under JNTUANANTAPUR).

SUBMITTED an official paper documentary on QUALITY OF EDUCATION IN INDIA AND SUGGESTIONS TO MODIFY THE SYSTEM to Central Human Resource Minister as participation for the first time from our college.

Extracurricular Activities

Convener of “STUDENT ACTIVITY COUNCIL” (SAC) in our college.

Coordinator for all student related events in the college.

TEAM LEADER for my academic project.

VLSI Projects

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the design.

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog.

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design.

Engineering Project

Automated Irrigation System through Wireless Sensor Network and GPRS Module

HDL: Embedded C

EDA Tools: Keil, Proteus, Flash Magic.

Hard ware Component: 8051 Micro Controller.

Description:An automated irrigation system was developed to optimize water use for agricultural crops. The system has a distributed wireless network of soil-moisture and temperature sensors placed in the root zone of the plants.

Responsibilities:

Architected the design.

Implemented the programming code using Embedded C.

Architected the class based verification environment using system Proteus.

Verified the programming model using Keil.

Implemented hardware design based on the Proteus layout.

Verified the proper working of the kit.

Personal Profile

Date of Birth : 05-03-1994

Father name : Yeddula Ramapathi

Other Languages Known : TELUGU, ENGLISH

E-Mail id : *******************@*****.***

Mobile number : 096********

Place: Bangalore

Date: 17/07/2015

(Yeddula shasidhar)

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