Android Developer

CHETHANA.K.C

E-mail : ***********@*****.***

Contact No. : +91-916*******

Address for Communication

#**, *** ***** ***, ****** New Thippasndra, HAL 3rd stage,

Bangalore - 560075

Permanent Address

T.A.P.M.C.S Rice mile, Sorab, Shivmoga,Karnataka - 571429,

Personal Information

Date of Birth : June.01,1989

Sex : Female

Marital Status : Single

Nationality : Indian

Language Proficiency

English, Kannada, Hindi

Objective

To Work In The Organization That Helps Me Contribute To The Growth Of The Organization By Leveraging My Skills In The Industry, And Enabling Me To Grow, By Providing Exposure To Challenging Tasks That Enable Constant Learning.

Current Experience

Organization: Aeronautical Development Establishment, DRDO, Bangalore

Designation: Contract Engineer

Period: March 2015 to Till date

Role: program Developer

Job Description:

TIFF to JPNG Conversion using QGSM

RUAV & TERCOM project Using QT creator

Basic ANDROID design using Eclipse

Education

Bachelor of Engineering

Period : 2009-2012

Subject : Electronics and Communication

Percentage : 68.61%

Institute :P.A College of Engineering, Mangalore

University: VTU, Belgaum

Diploma

Period: 2005-2008

Subjects : Electronics and Communication

Percentage : 63.60%

Institute: Government Polytechnic, Sorab

Board of Education: Board Of Technical Education

Secondary Education(10th/SSLC)

Period : 2004-2005

Subject : General

Percentage : 72.80%

Institute: S.C.D.S Girls High School, Sorab

Computer Literacy

Operating system: WINDOWS 7, 8, XP

Language: Basics in C,C++, JAVA, XML,Verilog.

Tools used: Turbo C, Eclipse, Android studio, VLSI design cadence tools.

Technical Course

Undergone training in ANDROID Development from DALLAS TECHNOLOGIES for a period of 3 months.

Academic Projects undertaken:

1.Title : New High-Speed CMOS Full Adder Cell of Mirror Design Style

Period : Feb 2012 – Apr 2012

Tools used : VLSI design cadence gpdk180 tools

Team size : 4

Description :

A new circuit of a high-speed CMOS full adder cell provides a higher speed of carry signal formation as compared to the known adders and, hence, allows achieving high speed of the N-bit adder device. The proposed cell has been compared to the other three basic cell (Conventional CMOS FA(CFAMS), Improved conventional CMOS FA(ICFAMS), CMOS FA based on the Transmission Gates(FABTG))

Academic/Non-Academic Achievement

Our project New High-Speed CMOS Full Adder Cell of Mirror Design Style got first prize in ISTE Group held project session in PACE Institution.

Our project New High-Speed CMOS Full Adder Cell of Mirror Design Style got selected for KSCST and our project team got money prize.

Obtained certificates acknowledging the participation in various cultural activities in school, college and taluk levels.

Extra Curricular Activities

Hobbies: Reading novels, Playing Badminton and chess.

Declaration

I hereby declare that above information is correct to the best of my knowledge and belief.

Place: Bangalore

(CHETHANA.K.C)

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