Technical Power

Santosh Kumar B

Email: *******.*******@*****.***

Tel: 897*******

Career Objective

Upcoming Visvesvaraya Technology University graduate offering a strong academic background in IT combined with excellent internship experience as a helpdesk analyst. Consistently recognized for technical troubleshooting skills used to rapidly and cost-effectively resolve challenging technical issues. Quickly learn and master new technology; equally successful in both team and self-directed settings; and proficient in a range of computer systems, languages, tools and testing methodologies.

Academic Credentials

M.Tech VLSI & ES

Bellary Institute of Technology and Management, Bellary

74.39%

Aug-2012

Spt-2014

B. E ECE

PDIT Hospet, Visvesvaraya Technology University, Belgaum.

62.50%

Jun-2007 ‘Jul-2010

Diploma

Department Of Technical Education Board- Bangalore.

63.05%

Apr-2004 May-2007

SSLC

Karnataka Secondary Education Examination Board- Bangalore

56.96%

Apr-2002

IT Skill set

Technical Tools

:

C, HTML, JavaScript, VHDL, Verilog, Hardware and Networking.

Operating system

:

Ubuntu, Mint, Red hat, Windows XP/7.

Software skills

:

Xilinx, Ltspice and Magic.

Project Work

Title

:

“analysis, verification and fpga implementation of Vedic multiplier in alu”

Role

:

A new technique faster & Provides perfect result.

Environment

:

Xilinx 7.1, Model Sims, FPGA kit Software and Windows OS

Description

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used Computation- Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip.

The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier.

In this work, Urdhva tiryakbhyam Sutra is applied to the binary number system and is used to design digital multiplier architecture. The architecture is built using the VERILOG® hardware description language and synthesised in Xilinx and simulated in Modelsim. This architecture is then implemented in the alu for multiplication.

.

Responsibilities

Devising stored procedures and functions for the entire application

Involving in designing, coding, Unit Testing.

Experience

Year

Professional

Organization

2010

Lecture

Govt Polytechnic college Koppal, Koppal-583231

2010-12

Hardware & Networking Engg.

VANAY STEEL PRVITE LTD. Koppal-583231

Personal Dossier

Date of Birth

-

24- Jul-1986

Father Name

-

Shankar.B

Mother Name

-

Savita.B

Marital Status

-

Single

Nationality

-

Indian

Languages known

Hobbies

Address

-

-

-

English, Hindi, Kannada & Telugu.

Playing Cricket & Chess, Browsing, Listening to music...

H/No: 7-1-21/27, Gavishree Nagar

Mata Hotel opposite

Koppal-583231. (Karnataka)

Declaration

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Date: Santosh Kumar B

Place: Koppal Signature

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