Project Training
Resume:
ROHIT GANGADHARAN
MTECH (VLSI DESIGN)
To obtain a position in semiconductor industry which emphasizes growth, creativity, and analytical thinking and to work in VLSI Domain where performance is rewarded with new responsibilities and to grow along with the organization as a core member of the same.
Programming Languages VHDL, C, Verilog HDL
Scripting Languages TCL, Shell, PERL
Software Tools Mentor Graphics –ModelSim
Cadence -Virtuoso, Encounter
Synopsis – Prime time
Labview
Platform Worked on windows XP/7 & Linux (Ubuntu, Redhat)
Extensive breadth in digital and CMOS fundamentals.
Acceptable proficiency in CMOS process flow and semiconductor device physics Contact
37-D, Pocket A-2
Mayur Vihar Phase-3 Delhi-96
E mail : *********@*****.***
2013-2015 Master of Technology in VLSI Design
Amity University, Noida
First Class with 7.27 CGPA
2009-2013 Bachelor of Technology in ECE
RCET, Thrissur Calicut University
First Class with 7.14 CGPA
2007 -2009 Senior Secondary (PCMB)
A.S.N Sr. Sec School, Delhi
Distinction with 81%
1997-2007 Secondary
K.E.S.S School, Delhi
Distinction with 85%
PROFILE
TECHNICAL SKILLS
EDUCATIONAL QUALIFICATION
Excellent grasping capability of new technologies
Strong hand in design rule requirements and CMOS process layers
Good understanding of synthesis, Physical Design flow, IR drop analysis, STA, fabrication process, ECO, DFM
Sound written and oral communication skills
Worked on Floorplanning, PnR flow, CTS, Routing, NDR rules, MMMC, ECO.
MTECH (Major Project)
Project 2 name: Block level implementation of Leon Processor Organization: Orange semiconductors Pvt.ltd
Role: Physical Design Trainee
Technology information:
Tt Technology used 45nm technology
No. of clocks 2
No. of instances 35000
No. of macros 4
No. of metal layers 9
Challenges faced: The whole PD flow was done till antenna (dangling wire) removal. The various challenges faced are congestion, timing violations and DRV’s, connectivity violations. The project also involved writing a Tcl script to add a buffer to the middle of a net to reduce hold violations.
Tool used: Cadence encounter tool (Cadence® Encounter® Digital Implementation (EDI) System). Project 1 name: Chip level implementation of DTMF chip. Organization: Orange semiconductors Pvt.ltd
Role: Physical Design Trainee
Technology information:
Tt Technology used 180nm technology
No. of clocks 2
No. of instances 9540
No. of macros 4
No. of metal layers 6
Challenges faced: The design actually worked at 14ns, which was constrained to 2ns and the whole PD flow was done till antenna (dangling wire) removal. The various challenges faced are high congestion, timing violations and DRV’s, connectivity violations. PROJECTS
Tool used: Cadence encounter tool (Cadence® Encounter® Digital Implementation (EDI) System). MTECH (Minor Project)
Project name: Design, modeling and simulation of “Silicon Photonic Crystal Modulator”. Duration: 6 weeks.
Summary: To design model and simulate a silicon photonic crystal modulator using a multi-physics tool “COMSOL”. The electron and hole concentration, electric potential, electric field variation of the modulator is noticed by varying the various parameters like materials, RI. BTECH Project
Project name: Mains Monitor
Duration: 6 Weeks
Summary: To build a circuit on bread board to monitor the electrical circuit of an industry or for domestic purpose. A predefined voltage range is set and any voltage below or above that range blows an alarm for a while and an inverter circuit provides the optimal voltage range required. Later the circuit was even implemented in my college.
Undergoing training from Orange Semiconductors ltd as a Physical Design trainee.
Completed training from HCL ltd. Noida in May 2013
Completed training from Hykon Power Electronics ltd. in February 2012.
Completed training from KELTRON electro ceramics ltd. in February 2012
Date of Birth 30th May, 1992
Current address Balaji PG, H-block, Koramangala near sony world Languages Hindi English Malayalam Tamil French
Fluent Fluent Native Intermediate Beginner
I do hereby declare that all the particulars made above are true to the best of my knowledge and belief. Place: Bangalore (ROHIT GANGADHARAN)
TRAINING & CERTIFICATION
PERSONAL DETAILS
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