FPGA Design Engineer with 10 years experience

CAREER OBJECTIVE: Seeking a challenging career in FPGA design and development, at a growing organization where my skills and creativity will be put to the best utilization, and to turn the challenges into opportunities and translate my potential into performance.

BRIEF PROFILE

Senior Design Engineer with 9 years of experience in ASIC/FPGA Front End Design.

Working as Senior Design Engineer at Hexosys SDN BHD (Technology partner of Teledyne Lecroy Corporation, USA) in Kuala Lumpur, Malaysia.

Possessing multiple entry B1/B2 visa for United States of America valid till April 2020.

High speed multi clock domain digital design for building very high speed data acquisition, protocol analysis and processing platforms.

Expertise in Xilinx and Altera IDE Tools & FPGAs.

Block and System level verification based on Test bench, BFM, Regression test

Strong lab experience using scopes, logic analyzers and Hardware in Loop System Co-Simulations.

Static Timing Analysis and Timing Closure and full FPGA Backend flow and debug of complex logic designs.

Expert in validation, bring up and debug of designs on FPGA.

TECHNICAL SKILLS

Hardware Design : ASIC/SoC & FPGA Design.

Protocols/Interfaces : FC 16G, FCoE/Ethernet 10G/40G/100G, Serial Rapid IO

(SRIO), DDR3/DDR2/LPDDR2, Serdes, PCIe, SPI, I2C,

Ethernet PCS/MAC, Microprocessor and peripheral interfaces.

HDL : VHDL, Verilog

EDA Design Tools : Xilinx ISE 12.4, Xilinx EDK 12.4, Xilinx SDK 12.4, Xilinx

System Generator 12.4, Xilinx Plan Ahead 12.4, Xilinx

Chipscope 12.4, FPGA Editor 12.4, AccelDSP,

Quartus II 14.0, SOPC Builder, DSP Builder, NIOS II IDE

7.0, Leonardo Spectrum 2000.1b, ModelSim PE 10.1a,

QuestaSim 10.1a, MATLAB 7.0.4.365 (R 14), Synplify

PRO 9.2.4

Debugging Tools : Xilinx ChipScope Pro, Altera Signal Tap II, Lecroy Signal

Scopes, HP Logic Analyzer, Lecroy Protocol Analyzers

FPGA : Altera Stratix V GX - SGXEA7H35C3GX - Xilinx Virtex-6

XC6VLX240T, Virtex-5 XC5VSX95T

XC6SLX150T, Spartan-6 XC6SLX45T, Spartan-3A

XC3S1400A, Spartan-3E XC3S1200E,

Stratix-V 5SGXEA7H35C3ES

Cyclone III, Cyclone II

CPLD : CoolRunner series, MAX II, MAX 7000, XC9500

Programming Languages : Exposure to C, C++

Scripting Languages : Cygwin Shell, Make file, TCL, Unix/Solaris shell.

Layout Editor : Mentor Graphics IC Station V 8.9-5.1

Physical verification Tool : IC Station suite (DRC, LVS, XELGA, ELDO)

WORK EXPERIENCE

1. Company Name : Hexosys SDN BHD, Kuala Lumpur, Malaysia (Technology partner of Teledyne Lecroy Corporation, USA)

Designation : Senior Design Engineer

Duration : From May 2011 till date

Key Responsibilities :

Responsible for micro-architecture design of the FPGA based on marketing requirements, specifications, performance and other constraints.

Responsible for designing RTL modules in Verilog/VHDL and designing, simulating and integrating to the top level module and optimizing the same to leverage the architectural features of the FPGA and extracting the best performance from the FPGA.

Currently working on 10G/40G/100G FCoE/Ethernet Protocol Analyzer design.

Responsible for design and verification at module and top level from synthesis, place and route to bring up and debug of design on target board and interact with software team to design the software interface.

2. Company Name : Enventure Technology Services Pvt Ltd, Bangalore.

Designation : Senior Design Engineer

Duration : From Feb 2010 till April 2011

Key Responsibilities :

Worked as a member of R&D team for Innovative Integration, California.

Responsible for designing RTL modules in VHDL and integrating to the top level module and optimizing the same to leverage the architectural features of the FPGA and extracting the best performance from the FPGA.

Involved in timing closure of timing critical designs and optimize the netlist to fit the design in the particular FPGA. This involves analyzing the timing report and constraining the design to achieve the timing and also usage of advanced optimization techniques to achieve the desired goal of area, timing or performance of the design.

Involved in designing test benches and BFMs to test the RTL code and ensure the desired operation from the FPGA based system along with the interfaced peripherals on the hardware board.

Involved in close interactions with the team at US and research and develop modules adhering to the standards and guidelines.

3. Company Name : Nu Horizons Electronics Asia Pte Ltd, Bangalore

Designation : Design Engineer

Duration : From July 2007 to January 2010

Key Responsibilities :

Responsible for architecting the client’s concept of design into an FPGA based system. This involves estimating the resource utilization for the modules and IPs involved, estimating the Fmax and feasibility of peripheral interfaces involved and choosing the best suitable FPGA for the application.

Responsible for designing particular modules and optimizing the same to leverage the architectural features of the FPGA and extracting the best performance from the FPGA.

Involved in timing closure of timing critical designs and optimize the netlist to fit the design in the particular FPGA. This involves analyzing the timing report and constraining the design to achieve the timing and also usage of advanced optimization techniques to achieve the desired goal of area, timing or performance of the design.

Review the design from RTL to schematic design to ensure the desired operation from the FPGA based system along with the interfaced peripherals.

4. Company Name : Achieva India Pte Ltd, Bangalore

Designation : Design Engineer

Duration : From August 2005 to June 2007

Key Responsibilities :

Responsible for designing particular modules and also designing FPGA systems to convert legacy designs based on microcontrollers and discrete parts to design an efficient system which leverages the flexibility and performance of FPGA to create a single chip and cost effective solution.

Worked on building FPGA based digital designs on Altera based systems.

Involved in reviewing the design from RTL to schematic design to ensure the desired operation from the FPGA based system along with the interfaced peripherals

TECHNICAL TRAINING

Advanced Post Graduate Diploma in VLSI design (United Technologies, Bangalore from June ’05 to August ’05)

Training on Synplicity EDA tools (Synplify, Synplify Pro, Certify).

Training on Mentor Graphics EDA tools (ModelSim, Questasim).

Training on Embedded System Development.

Training on DSP Design using System Generator

Training on Designing with Ethernet MAC’s.

AWARDS & ACHIEVEMENTS

Presented seminar on “The Cell Matrix: An Architecture for Nano Computing” during the course of B.E.

Participated and won in many inter-school sports activities at school level.

Secured 27th rank in state level SCIENCE APTITUDE TEST held in 1999.

Selected as umpire in international level SATELLITE MASTER’S TENNIS TOURNAMENT held at Kannur in 1998.

Participated and won in extra curricular activities like essay, poem writing, calligraphy, music, poster designing, drawing held at school level.

Awarded the Design Engineer of the year for the financial year ’09.

ACADEMIC BACKGROUND

Degree

Institute / Board/ University

Year of Passing

Area

B.E.

Nitte Mahalinga Adyanthaya Memorial Institute of Technology, Nitte (VTU, Belgaum)

2005

Electronics & Communication

XII

Chinmaya Vidyalaya, Kannur(CBSE)

2001

Science (PCMB)

X

Chinmaya Vidyalaya, Kannur(CBSE)

1999

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PROJECT WORK

1.Product Development for Teledyne Lecroy Corporation

Project Title : 10G/40G/100G FCoE/ Ethernet Protocol Analyzer

Language : Verilog

Device : Altera Stratix-V GX - 5SGXEA7H35C3

Project Profile : This platform is used as 8 port Analyzer to analyze the 10G/40G FCoE/Ethernet protocol traffic between Host (Server) and Device (Disk Shelf) with a trace capture capacity of 64 GB. This involves 2 Stratix 5 GX FPGA for complex protocol analysis and capture of traffic on the DDR3 memories on board along with multiple interfaces and external peripherals.

1.Involved in discussions with the marketing team to study the viability of required features to be supported with the product.

2.Involved in choosing the most suitable FPGA and designing the micro architecture for the project.

3.Designed the Memory Interface module which is the main back bone of the system which interprets and converts incoming data processed by the Serdes into memory block packets. It handles the triggering and hardware based packet filtering along with various other essential features of the system. It can handle Auto Negotiation data, different types of frames and order sets along with different events of bus conditions on the line.

4.Designed the Memory Management unit which is responsible for transferring data packets from the Memory Interface to the DDR3 interface and then read back the same via host interface to PCI Express to the Intel Atom processor on board to be displayed by the host software on the PC.

5.Designed the DDR3 interface running at 466 Mhz to interface to the 4 x DDR3 SODIMMs of 4 GB each on both the FPGA, thus capacitating 64 GB of data collection from the 4 ports.

6.Designed the Smart module which is an innovative module which can sense the rate of traffic on each line and switch the storage of data among the 4 DDR3 memories for efficient usage of space.

7.Involved in interactions with the software and firmware team to interface the hardware to the software and firmware design.

8.Involved in synthesis, P & R and timing closure of the design and also bring up of the interfaces and the FPGA design on the target board.

9.Designed the 40G Serdes modules for Marker alignment, Deskew control and other related logic for the 40G version of the Analyzer.

10.Designed the Pattern Generator and Analyzer Processing Unit for the 40G version of the Analyzer.

11.Designed Time Stamp generation logic to achieve Time Stamp resolution of 1ns (Design clocked at 1 Ghz).

12.Designed many other feature additions to the product according to end client requirements.

13.Involved in System test and integrated full system rigorous tests of the product.

14.Tested the product with different Servers, Disk shelves, switches, network interface cards and protocol testers from NetApp, HP, Dell, Mellanox, Ixia, SANBlaze, and Xena.

2.Product Development for Innovative Integration

Project Title : X6 RX Baseband Receiver Platform

Language : VHDL

Device : Xilinx Virtex 6 - XC6VLX240T

Project Profile : This platform is used as a Baseband Receiver platform. This involves a Virtex 6 FPGA for complex digital processing along with multiple interfaces external peripherals.

1.Designed the ADC interface for National ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs. Also designed the SPI interface used to configure the internal registers of the ADC. Designed the Wishbone interface register and interface to the PCIE interface. Also designed the BFM emulating the ADC device and the test bench to test the interface.

2.Designed the Wishbone system which is used for communication of the software on the Host PC to the modules on the FPGA. Every module has an offset address and a set of registers which are controlled by the Wishbone system. Designed the test bench to test the same.

3.Designed the Packetizer module which is used to packetize the data in 128 bit mode compliant to the 8 lane PCI Express Gen 2 and send to the Host PC for further processing and analysis. Designed the test bench to test the same.

4.Designed the Alert module which is used to transfer alerts to and from the Host to the modules and designed the test bench to test the same.

5.Designed an interface to the LM96163 temperature sensor IC which works on the I2C interface and is used as a protection to the platform from over temperature. Designed and tested the interface along with WB system and BFM.

6.Designed an interface for the DS2432 which is a 1 wire based security chip which is used to protect the IPs on the device from read back and reverse engineering.

7.Designed the configuration interface for the board with a configuration flash, and designed a controller for the SelectMAP mode configuration. The controller is designed on a CPLD for remote bit stream updation from the host PC with protection from accidental re-configuration.

8.Designed an interface for the 32-Megabit SPI based Data flash from Atmel with part number AT45DB321. Designed and tested the interface along with WB system and BFM.

9.Designed the X6 RX top level module and test bench with integration of all the sub modules and placement and timing constraints.

10.Customized the Serial Rapid IO core from Xilinx to be integrated to the X6 RX.

3.Client Project (Nu Horizons)

Project Title : Portable Ultrasound

Client : Siemens, Bangalore.

Language : Verilog HDL.

Project Profile : Designed and implemented the UDP Ethernet framer and deframer to establish a point to point link for communication between the laptop and the ultrasound board. Optimized the entire design to reduce the power consumption of the design and enhanced the life span of the pen cell battery on which the board has to sustain.

4.Client Project (Nu Horizons)

Project Title : Data Acquisition Card

Client : Siemens, Bangalore.

Language : Verilog HDL.

Project Profile : Designed and implemented a 14th Order IIR filter in HDL. Identified a stable filter structure that helps best to minimize the errors that get accumulated in the filter. Leveraged the benefits of DSP48 blocks in Virtex 4 SX part to achieve a fmax of 263 Mhz for the filter, and also designed a soft reset system restart the filter every few seconds to flush out the accumulated errors. Also customized XAPP866 to meet the required timing and establish the high speed ADC interface by monitoring and adjusting ISERDES using chipscope.

5.Client Project (Nu Horizons)

Project Title : Emulation Platform

Client : AMD, Bangalore.

Language : VHDL.

Project Profile : Designed and implemented an EDK based system involving the PowerPC 440 core and established 1G Ethernet based system. Also designed an application to read and write values of the configuration registers of the Marvel PHY on board to facilitate the changing of the register values using the application code using the MDC/MDIO interface, thus avoiding the tradition method of the hardwiring and providing external switches on board for the purpose. And also helped to design modules to test various other interfaces on board.

6.Client Project (Nu Horizons)

Project Title : Ethernet over 4 E1

Client : Cygnus Microsystems, Hyderabad.

Language : VHDL.

Project Profile : Designed and implemented the E1 framer and deframer and interfaced to the Xilinx TEMAC. The TEMAC running at 10 mbps data rate is evenly sent over 4 E1s at a data rate of 2.048 mbps thus giving a throughput of 8.192. The data received from TDM lines is realigned and sent on the Ethernet using the TEMAC.

7.Client Project (Nu Horizons)

Project Title : IP Phone

Client : Allo.com, Bangalore.

Language : VHDL.

Project Profile : Supported in implementing the HDL design of the modules which is a part of the IP Phone thereby interfacing the different ASIC’s on the board.

8.Client Project (Nu Horizons)

Project Title : Back Haul Radio

Client : Shyam Telecom, Delhi.

Language : VHDL.

Project Profile : The project aims at providing telecom access to the people of rural India. Designed and implemented the framer and deframer for the Back Haul Radio which is used in the GSM network for transmission of voice data. The 8 bits of digitized voice data of 46 users is time multiplexed into 48 channels and then and transmitted over the wireless network 1000 times per second; thus making a line rate of 384 Kbps for communication.

9.Client Project (Achieva)

Project Title : Totaliser for Electronic Voting Machine

Client : Bharath Electronics, Bangalore.

Language : Verilog HDL.

Project Profile : Designed and implemented a Totaliser for the Electronic Voting Machine wherein the data from the EVM is interfaced to the NIOS II soft core processor through the RS232 UART connected using a DB-9 connector and interfaced with the EP2C5F256C8 after a level converter. The board has a 20x20 keyboard and then same data has to be displayed on the 16x2 LCD module.

10.Client Project (Achieva)

Project Title : Display System for Petrol Dispensers

Client : MIDCO, Mumbai.

Language : Verilog HDL.

Project Profile : Designed and implemented the Display System for the Petrol Dispensers which has an array of 16 Segment Displays. The design is basically an interface for these displays and is implemented on MAX II generation low cost CPLD’s. The main advantage is the reduction of the board size as they were earlier using of-the-shelf ASIC’s, one for each display.

11. Major Project (United Technologies)

Project Title : SDRAM CONTROLLER.

Company : United Technologies, Bangalore.

Language : Verilog HDL.

Project Profile : SDRAM Controller provides the user with a simplified interface to

Industry standard memory devices. The accessing of SDRAM devices is made as simple as

possible. The controller does initialization and refresh. The controller has been designed to

interface Micron SDRAM (MT48LC2M8A1) and Motorola 68040v processor. All the timing

considerations are met in the design for the read, write and refresh operations. This design can

be upgraded to a universal SDRAM controller to interface between processors and memories

of any make.

12. Major Project (During 8th Semester of B.E)

Project Title : VHDL Implementation of Huffman Encoder/Decoder.

Company : Silicon Micro Systems, Bangalore.

Language : VHDL

Project Profile : Designed and implemented Encoder/Decoder for the purpose of

Compression/Decompression of data using Huffman Algorithm. The Huffman codes were

assigned using a table which used a common probability of occurrence of English text. The

design was verified for functional correctness with testbenches and simulated the same using

ModelSim SE-EE 5.4e. This can be used for half duplex Transmission/Reception of data.

CO-CURRICULAR ACTIVITIES AND HOBBIES

Organised various events at school and college level.

Participated in inter-batch socials at college level.

Implementing small electronic circuits on circuit boards.

Reading, listening to music, painting, penning poems and articles.

Playing chess, football, cricket and badminton.

PERSONAL TRAITS

Ability to work as an active team member and as an individual contributor.

Perseverance and never give up attitude.

Ability to grasp quickly, keen learner and self starter.

Hardworking and always willing to accept challenges.

PERSONAL PROFILE

Date of Birth : 07th May 1983

Marital Status : Married

Passport : Indian

US Visa : Multiple Entry B1/B2 visa valid up to April 2020.

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