Pabitra Kumar Mohapatra
Cell No: +91-720*******
Email: **************@*****.***
CARRIER OBJECTIVE
To be associated with a progressive organization which can provide me with a dynamic work sphere to extract my inherent skills as a Professional, use and develop my Aptitude to further the organization’s objectives and also attain my career targets in the progress.
PROFESSIONAL QUALIFICATION
M.Tech in VLSI DESIGN from CENTURION UNIVERSITY OF TECHNOLOGY & MANAGEMENT (CUTM), BHUBANESWAR, ODISHA.
B.E in Electronics & Communication from KNSIT affiliated to VTU, KARNATAKA.
INTERMEDIATE from LN COLLEGE, BALASORE, ORISSA.
S.S.C from SC HIGH SCHOOL (Board of Secondary Education), ORISSA.
IMPORTANT TRININING & SEMINAR
Attended Robotics seminar in VIT College, TN.
Attended a workshop on DIGITAL IMAGE PROCESSING in College.
Completed Professional Course CORE JAVA/J2EE in JDOT, Bangalore.
SOFTWARE KNOWLEDGE
Operating system : MS Windows Family
Database : MySQL,Oracle, JDBC
Software : Xilinx ISE, MICROWIND,MULTISIM
Hardware Language : VHDL, VERILOG
Technical interests : IC LAYOUT, PCB DESIGN
Languages : Core JAVA
PROJECT HIGHLIGHTS
ACADEMIC PROJECT (B.E)
Project Title: ACCIDENT MONITERING CUM INTEMATOR FOR VECHICULAR NETWORK
Description: This project deals with the wireless data communication between base station and road vehicles and helps to make smooth traffic flow on the road and also prevents further casualties around already happened accident.
Role: Project trainee
Responsibilities: Project Development activities such as Requirements Gathering, Designing and Coding.
Technical Specifications:
89s52 microcontroller and DTMF and microcontroller language used
ACADEMIC PROJECT (M.TECH)
Title: VHDL Implementation of noval low power squaring circuit using YTVY algorithm of vedic mathmatics.
Objective: A innovative idea of a squaring circuit without using multiplier is suggested in this paper. In this paper, I have implemented a novel algorithm Yavadunam Tavadunikrtya Vargarica Yojayet (YTVY) of ancient vedic mathematics for the squaring operation circuit. The main advantage of this paper is that no multiplier is used for the squaring circuit. The circuit is designed with the help of VHDLlanguages and synthesized in Xilinx ISE Design Suite 14.1.
Project guide: Prof. Siba Kumar Panda (Dept of ETC,CUTM,Bhubaneswar)
PUBLICATIONS
[1].Pabitra Ku. Mahapatra,Siba Kumar Panda etal. “VHDL implementation of a Novel Low Power Squaring Circuit Using YTVY Algorithm of Vedic Mathematics” International Journal of Emerging Trends in Science and Technology(IJETST) Vol-02,Issue-03,March-2015,ISSN 2348-9480, Pages 2139-2146.
PERSONAL DETAILS
• Father’s Name : Ananta Kumar Mohapatra
• Date of Birth : 17th FEB 1988
• Gender : Male
• Nationality : Indian
• Languages : English, Oriya & Hindi
• Permanent Address : Gengutia, Baliapal, Balasore, Odisha- 756026
• Strength : Quick learner, Hardworking & Self-confident
• Hobbies : Playing Cricket, Watching movies
Place: ODISHA (Pabitra Kumar Mohapatra)