Verilog,VHDL,C,Shell scripting,Perl scripting

NILESH KUMAR CHATURVEDI

Mobile: +91-941*******, Email: ******************@*****.***

Education

Course Institute Passing Year Percentage/CG

PA

M.Tech(VLSI

Design)

Gautam Buddha University,Greater Noida

(U.P.)

2015 7.8 CGPA

B.Tech(ECE) SCRIET,C.C.S. University Meerut,U.P. 2013 75.5% XII N.B.Inter college,Jaunpur,U.P. 2008 58.4%

X N.B.Inter college,Jaunpur,U.P. 2006 69.6%

Technical Skills

Programming Languages: Verilog, VHDL, C

Scripting Languages: Shell Scripting, Perl

Engineering Tool: Modelsim, Questasim, Xilinx ISE, Cadence Virtuoso, Tanner tool, Comsol Multiphysics Operating Systems:Windows, Linux

Project Experience

Implementation of Folded Pipelined Fast Fourier Transform Core (Aug’ 2014-Apr’ 2015 )

Used the Pease algorithms for FFT Architecture in order to improve the speed of DSP.

Wrote algorithms in Verilog HDL at RTL for Architecture.

Verified with several test benches and synthesized in Xilinx ISE

The design has been implemented on a range of FPGAs to compare the performance.

Tool used – Xilinx ISE, Modelsim, FPGA

Common-Gate Low-Noise Amplifier (LNA) (Jan’ 2014-Apr’ 2014 )

A fully integrated capacitor cross-coupled CGLNA implemented in 90–nm CMOS validates the gm- boosting technique.

Constructed schematics for each part of the circuits with Cadence, analyzed key parameters including the Noise Figure,S-Parameter,Voltage gain.

Implemented the whole layout in Virtuoso with DRC, LVS clean.

Tool used – Cadence Virtuoso

High Electron Mobility Transistor (HEMT) (Jan’ 2013-Apr’ 2013 )

Designed of GaN HEMT using COMSOL Multiphysics tool

Analyse Thermal behaviour of the multidimensional GATE and substrate of GaN HEMT.

Tool used – Comsol Multiphysics

Minor project:

1-Traffic Light Controller using VHDL

Developed code using VHDL and verified with several test benches in Modelsim and synthesized in Xilinx ISE

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