Engineer Engineering

SUGANYA S

N* * Subramanian Nagar,

Reddipalayam road

Thanjavur 613009

Contact: +91-962*******

Email: *********@*****.***

A self motivated Engineer with innovative ideas and willing to involve myself in challenging research works related to VLSI design with passion and hard work.

Summary

Good knowledge in handling simulation and synthesis tools like Xilinx, Modelsim Quartus II.

Have hands on experience in Cadence Nc launch (Digital Design)

Have knowledge of writing HDL (Verilog) codes for digital circuits.

Good understanding of VLSI system design concepts and having clear knowledge about Digital electronics.

Technical Expertise

Languages: Verilog, VHDL

OS: Windows.

H/W Platforms: Altera (DE1,DE2), Spartan 3E.

IDE: Matlab.

Basics of C language.

ORCAD – Capture, Pspice, PCB Editor.

Recent Projects

Project:

DYNAMIC POWER REDUCTION FOR VLSI CIRCUIT USING DELAY INSERTION METHODOLOGY WITH EMBEDDED TRANSITION INVERSION

Programming Language: HDL (Verilog)

Tools : Modelsim Quartus II, Hardware : Altera DE1

Academic Records

DEGREE/EXAM

Institution/school

Year of passing

Percentage

M.E VLSI DESIGN

SAVEETHA ENGINEERING COLLEGE

2015

72*%

B.TECH ECE

PONNAIYAH RAMAJAYAM INSTITUTE OF SCIENCE AND TECHNOLOGY(PRIST)UNIVERSITY

2013

75%

H.S.S

SACRED HEART GIRLS HR.SEC.SCHOOL THANJAVUR

2009

64%

SSLC

SHRI VENKATESHWARA MATRICULATIONHR.SEC.SCHOOL THANJAVUR

2007

61 %

Conferences and Publications

Published paper entitled “DYNAMIC POWER REDUCTION FOR VLSI CIRCUIT USING DELAY INSERTION METHODOLOGY WITH EMBEDDED TRANSITION INVERSION” in International Journal Of Applied Engineering Research which is referred under Anna University listed Annexure II journals.

Personal Information

Father’s Name: S. Subramanian

Nationality: Indian

Language: Tamil (proficient), English (proficient), Telugu (Basic)

Place : chennai

Dated : S. suganya

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